[U-Boot,v2,14/20] riscv: Add exception codes for xcause register

Message ID 1544192072-28764-15-git-send-email-bmeng.cn@gmail.com
State Superseded
Delegated to: Andes
Headers show
Series
  • riscv: Adding RISC-V CPU and timer driver
Related show

Commit Message

Bin Meng Dec. 7, 2018, 2:14 p.m.
This adds all exception codes in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/riscv/include/asm/encoding.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Auer, Lukas Dec. 10, 2018, 11:51 p.m. | #1
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds all exception codes in encoding.h.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> 
> Changes in v2: None
> 
>  arch/riscv/include/asm/encoding.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

Patch

diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index c910d5c..e6d905a 100644
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -85,6 +85,21 @@ 
 #define IRQ_COP		12
 #define IRQ_HOST	13
 
+#define CAUSE_MISALIGNED_FETCH		0
+#define CAUSE_FETCH_ACCESS		1
+#define CAUSE_ILLEGAL_INSTRUCTION	2
+#define CAUSE_BREAKPOINT		3
+#define CAUSE_MISALIGNED_LOAD		4
+#define CAUSE_LOAD_ACCESS		5
+#define CAUSE_MISALIGNED_STORE		6
+#define CAUSE_STORE_ACCESS		7
+#define CAUSE_USER_ECALL		8
+#define CAUSE_SUPERVISOR_ECALL		9
+#define CAUSE_MACHINE_ECALL		11
+#define CAUSE_FETCH_PAGE_FAULT		12
+#define CAUSE_LOAD_PAGE_FAULT		13
+#define CAUSE_STORE_PAGE_FAULT		15
+
 #define DEFAULT_RSTVEC		0x00001000
 #define DEFAULT_NMIVEC		0x00001004
 #define DEFAULT_MTVEC		0x00001010