[U-Boot,v2,11/20] riscv: Enlarge the default SYS_MALLOC_F_LEN

Message ID 1544192072-28764-12-git-send-email-bmeng.cn@gmail.com
State Superseded
Delegated to: Andes
Headers show
  • riscv: Adding RISC-V CPU and timer driver
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Commit Message

Bin Meng Dec. 7, 2018, 2:14 p.m.
Increase the heap size for the pre-relocation stage, so that CPU
driver can be loaded.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

Changes in v2: None

 arch/riscv/Kconfig | 3 +++
 1 file changed, 3 insertions(+)


diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 39ca2d8..c45e4d7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,4 +113,7 @@  config RISCV_RDTIME
 	  standard rdtime instruction. This is the case for S-mode U-Boot, and
 	  is useful for processors that support rdtime in M-mode too.
+	default 0x1000