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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id f6sm5206070pfg.188.2018.12.07.06.09.47 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Dec 2018 06:09:48 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Fri, 7 Dec 2018 06:14:27 -0800 Message-Id: <1544192072-28764-16-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544192072-28764-1-git-send-email-bmeng.cn@gmail.com> References: <1544192072-28764-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v2 15/20] riscv: Add indirect stringification to csr_xxx ops X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" With current csr_xxx ops, we cannot pass a macro to parameter 'csr', hence we need add another level to allow the parameter to be a macro itself, aka indirect stringification. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v2: - new patch to add indirect stringification to csr_xxx ops arch/riscv/include/asm/csr.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 29624fd..86136f5 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -61,10 +61,12 @@ #ifndef __ASSEMBLY__ +#define xcsr(csr) #csr + #define csr_swap(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -73,7 +75,7 @@ #define csr_read(csr) \ ({ \ register unsigned long __v; \ - __asm__ __volatile__ ("csrr %0, " #csr \ + __asm__ __volatile__ ("csrr %0, " xcsr(csr) \ : "=r" (__v) : \ : "memory"); \ __v; \ @@ -82,7 +84,7 @@ #define csr_write(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrw " #csr ", %0" \ + __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -90,7 +92,7 @@ #define csr_read_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -99,7 +101,7 @@ #define csr_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrs " #csr ", %0" \ + __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -107,7 +109,7 @@ #define csr_read_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -116,7 +118,7 @@ #define csr_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrc " #csr ", %0" \ + __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ })