[U-Boot,v2,15/20] riscv: Add indirect stringification to csr_xxx ops

Message ID 1544192072-28764-16-git-send-email-bmeng.cn@gmail.com
State Superseded
Delegated to: Andes
Headers show
Series
  • riscv: Adding RISC-V CPU and timer driver
Related show

Commit Message

Bin Meng Dec. 7, 2018, 2:14 p.m.
With current csr_xxx ops, we cannot pass a macro to parameter
'csr', hence we need add another level to allow the parameter
to be a macro itself, aka indirect stringification.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- new patch to add indirect stringification to csr_xxx ops

 arch/riscv/include/asm/csr.h | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

Comments

Auer, Lukas Dec. 10, 2018, 11:52 p.m. | #1
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> With current csr_xxx ops, we cannot pass a macro to parameter
> 'csr', hence we need add another level to allow the parameter
> to be a macro itself, aka indirect stringification.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> 
> ---
> 
> Changes in v2:
> - new patch to add indirect stringification to csr_xxx ops
> 
>  arch/riscv/include/asm/csr.h | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
> 

Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

Patch

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 29624fd..86136f5 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -61,10 +61,12 @@ 
 
 #ifndef __ASSEMBLY__
 
+#define xcsr(csr)	#csr
+
 #define csr_swap(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrrw %0, " #csr ", %1"		\
+	__asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1"	\
 			      : "=r" (__v) : "rK" (__v)		\
 			      : "memory");			\
 	__v;							\
@@ -73,7 +75,7 @@ 
 #define csr_read(csr)						\
 ({								\
 	register unsigned long __v;				\
-	__asm__ __volatile__ ("csrr %0, " #csr			\
+	__asm__ __volatile__ ("csrr %0, " xcsr(csr)		\
 			      : "=r" (__v) :			\
 			      : "memory");			\
 	__v;							\
@@ -82,7 +84,7 @@ 
 #define csr_write(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrw " #csr ", %0"		\
+	__asm__ __volatile__ ("csrw " xcsr(csr) ", %0"		\
 			      : : "rK" (__v)			\
 			      : "memory");			\
 })
@@ -90,7 +92,7 @@ 
 #define csr_read_set(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrrs %0, " #csr ", %1"		\
+	__asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1"	\
 			      : "=r" (__v) : "rK" (__v)		\
 			      : "memory");			\
 	__v;							\
@@ -99,7 +101,7 @@ 
 #define csr_set(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrs " #csr ", %0"		\
+	__asm__ __volatile__ ("csrs " xcsr(csr) ", %0"		\
 			      : : "rK" (__v)			\
 			      : "memory");			\
 })
@@ -107,7 +109,7 @@ 
 #define csr_read_clear(csr, val)				\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrrc %0, " #csr ", %1"		\
+	__asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1"	\
 			      : "=r" (__v) : "rK" (__v)		\
 			      : "memory");			\
 	__v;							\
@@ -116,7 +118,7 @@ 
 #define csr_clear(csr, val)					\
 ({								\
 	unsigned long __v = (unsigned long)(val);		\
-	__asm__ __volatile__ ("csrc " #csr ", %0"		\
+	__asm__ __volatile__ ("csrc " xcsr(csr) ", %0"		\
 			      : : "rK" (__v)			\
 			      : "memory");			\
 })