[U-Boot,v2,19/20] riscv: Return to previous privilege level after trap handling

From: Bin Meng <bmeng.cn@gmail.com>
To: Rick Chen <rick@andestech.com>, Simon Glass <sjg@chromium.org>,
	Lukas Auer <lukas.auer@aisec.fraunhofer.de>,
	Anup Patel <anup@brainfault.org>,
	U-Boot Mailing List <u-boot@lists.denx.de>
Date: Fri,  7 Dec 2018 06:14:31 -0800
Message-Id: <1544192072-28764-20-git-send-email-bmeng.cn@gmail.com>
In-Reply-To: <1544192072-28764-1-git-send-email-bmeng.cn@gmail.com>
References: <1544192072-28764-1-git-send-email-bmeng.cn@gmail.com>
Subject: [U-Boot] [PATCH v2 19/20] riscv: Return to previous privilege level
	after trap handling
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Message ID	1544192072-28764-20-git-send-email-bmeng.cn@gmail.com
State	Superseded
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Bin Meng <bmeng.cn@gmail.com> To: Rick Chen <rick@andestech.com>, Simon Glass <sjg@chromium.org>, Lukas Auer <lukas.auer@aisec.fraunhofer.de>, Anup Patel <anup@brainfault.org>, U-Boot Mailing List <u-boot@lists.denx.de> Date: Fri, 7 Dec 2018 06:14:31 -0800 Message-Id: <1544192072-28764-20-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1544192072-28764-1-git-send-email-bmeng.cn@gmail.com> References: <1544192072-28764-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v2 19/20] riscv: Return to previous privilege level after trap handling Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	riscv: Adding RISC-V CPU and timer driver \| expand [U-Boot,v2,00/20] riscv: Adding RISC-V CPU and timer driver [U-Boot,v2,01/20] riscv: add Kconfig entries for the code model [U-Boot,v2,02/20] dm: cpu: Add timebase frequency to the platdata [U-Boot,v2,03/20] riscv: qemu: Create a simple-bus driver for the soc node [U-Boot,v2,04/20] cpu: Add a RISC-V CPU driver [U-Boot,v2,05/20] timer: Add generic driver for RISC-V privileged architecture defined timer [U-Boot,v2,06/20] riscv: ax25: Hide the ax25-specific Kconfig option [U-Boot,v2,07/20] riscv: Introduce a Kconfig option for machine mode [U-Boot,v2,08/20] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor [U-Boot,v2,09/20] riscv: Implement riscv_get_time() API using rdtime instruction [U-Boot,v2,10/20] riscv: qemu: Add platform-specific Kconfig options [U-Boot,v2,11/20] riscv: Enlarge the default SYS_MALLOC_F_LEN [U-Boot,v2,12/20] riscv: Probe cpus during boot [U-Boot,v2,13/20] riscv: Add CSR numbers [U-Boot,v2,14/20] riscv: Add exception codes for xcause register [U-Boot,v2,15/20] riscv: Add indirect stringification to csr_xxx ops [U-Boot,v2,16/20] riscv: Do some basic architecture level cpu initialization [U-Boot,v2,17/20] riscv: Move trap handler codes to mtrap.S [U-Boot,v2,18/20] riscv: Fix context restore before returning from trap handler [U-Boot,v2,19/20] riscv: Return to previous privilege level after trap handling [U-Boot,v2,20/20] riscv: Adjust the _exit_trap() position to come before handle_trap()

[U-Boot,v2,19/20] riscv: Return to previous privilege level after trap handling

Commit Message

Patch