[U-Boot,v2,19/20] riscv: Return to previous privilege level after trap handling

Message ID 1544192072-28764-20-git-send-email-bmeng.cn@gmail.com
State Superseded
Delegated to: Andes
Headers show
Series
  • riscv: Adding RISC-V CPU and timer driver
Related show

Commit Message

Bin Meng Dec. 7, 2018, 2:14 p.m.
At present the trap handler returns to M-mode only. Change to
returning to previous privilege level instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---

Changes in v2: None

 arch/riscv/cpu/mtrap.S | 8 --------
 1 file changed, 8 deletions(-)

Patch

diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index da307e4..407ecfa 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -68,14 +68,6 @@  trap_entry:
 	jal handle_trap
 	csrw MODE_PREFIX(epc), a0
 
-#ifdef CONFIG_RISCV_SMODE
-	/* Remain in S-mode after sret */
-	li t0, SSTATUS_SPP
-#else
-	/* Remain in M-mode after mret */
-	li t0, MSTATUS_MPP
-#endif
-	csrs MODE_PREFIX(status), t0
 	LREG x1,   1 * REGBYTES(sp)
 	LREG x3,   3 * REGBYTES(sp)
 	LREG x4,   4 * REGBYTES(sp)