From patchwork Fri Dec 7 14:14:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1009451 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BN86tttA"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43BDvw35vTz9rxp for ; Sat, 8 Dec 2018 01:13:16 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E813BC2271C; Fri, 7 Dec 2018 14:12:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9D3C8C22752; Fri, 7 Dec 2018 14:10:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 72B70C22745; Fri, 7 Dec 2018 14:09:50 +0000 (UTC) Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by lists.denx.de (Postfix) with ESMTPS id 99C20C226F7 for ; Fri, 7 Dec 2018 14:09:43 +0000 (UTC) Received: by mail-pg1-f194.google.com with SMTP id w7so1767125pgp.13 for ; Fri, 07 Dec 2018 06:09:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=Ti2tWUSJdtW9UQvIG+TZ28RsuFcL7yxOTJCX6NqCkD8=; b=BN86tttAD0gs9RT8dhlrC/Z5qMhox5PiQacM0l7gDeh8unnkyHwCB6/BwmWRJWQRoK mnh9FmElHcQfX218pjhMevjK0LxTmKzmYd/Np/xpzPHzHGiiBl6jGCnHgA5dk43bCqbD LgptwxOIN0ossfPJwEdzcTSHyuDheYBf9X0gCt+VUa3CoeGNs2EbRYJ0r4+MXFM4gWF/ i+SF1VHVi+/ktKPoFL6fMSX1rmosK3U9pigejV40MWt4spHMy6TvaVBN/wtqgkgho4YK 6hp29/GS7ifrbn3Iw6jcmUf6WUywC+0Ky81jUWsf22fwWnV5twX28tHGkrRUklV8hTzz Y5Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Ti2tWUSJdtW9UQvIG+TZ28RsuFcL7yxOTJCX6NqCkD8=; b=YKOF2pBm7g7lG/VKcB5aWna3zB31VMiluKCaQdgiTU+lX4zzmfi+97diSgTTw6MpSQ K5x68sRFuuA4Gl19UyR7OJn3b4R6oVa2w6D5aTkX0fEgZoOewng7DP/oL7d8AagHVG+y PjPn5d2OFKoLttNOhpaqIdPfBXCrypV61H6wnwgDFXYMqegy/VTYyxk6ADjv+pAgnQjI z7LTk0DMScOKTO5MaBxeIc6E3JNjYDyY0edzVXHcLuAZx3OI23xulymVnvn42jbCJ6Fi y24YviQQ206O96nmmqeUh2j1mY994QqP6kn9cpJlej5O4KiZa2OWdIIv4y2SAixaXLDl ax4g== X-Gm-Message-State: AA+aEWYj850PigetxW9P6mO6fdE0+iDJomm9FdG0A52M+SQvqhioos+W hwmdxrkHOiN4BQdt5O7gvSo= X-Google-Smtp-Source: AFSGD/WTl1x+Wd/qbuzy7Plh/2U1lPUB3MJfUSkz1Wz7sw8vOMPrdQiuUE+TI7vG01OJfHJX6RgSpg== X-Received: by 2002:a63:441e:: with SMTP id r30mr2108605pga.128.1544191782302; Fri, 07 Dec 2018 06:09:42 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id f6sm5206070pfg.188.2018.12.07.06.09.41 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Dec 2018 06:09:41 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Fri, 7 Dec 2018 06:14:21 -0800 Message-Id: <1544192072-28764-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544192072-28764-1-git-send-email-bmeng.cn@gmail.com> References: <1544192072-28764-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v2 09/20] riscv: Implement riscv_get_time() API using rdtime instruction X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Anup Patel This adds an implementation of riscv_get_time() API that is using rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. Signed-off-by: Anup Patel Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v2: - incorporated and reworked Anup's S-mode timer patch @ http://patchwork.ozlabs.org/patch/1006663/ arch/riscv/Kconfig | 8 ++++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/rdtime.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) create mode 100644 arch/riscv/lib/rdtime.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f513f52..7dc6e3f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -104,4 +104,12 @@ config SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config RISCV_RDTIME + bool + default y if RISCV_SMODE + help + The provides the riscv_get_time() API that is implemented using the + standard rdtime instruction. This is the case for S-mode U-Boot, and + is useful for processors that support rdtime in M-mode too. + endmenu diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b13c876..edfa616 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o +obj-$(CONFIG_RISCV_RDTIME) += rdtime.o obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-y += interrupts.o obj-y += reset.o diff --git a/arch/riscv/lib/rdtime.c b/arch/riscv/lib/rdtime.c new file mode 100644 index 0000000..b16680f --- /dev/null +++ b/arch/riscv/lib/rdtime.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Anup Patel + * Copyright (C) 2018, Bin Meng + * + * The riscv_get_time() API implementation that is using the + * standard rdtime instruction. + */ + +#include + +/* Implement the API required by RISC-V timer driver */ +u64 riscv_get_time(void) +{ +#ifdef CONFIG_64BIT + u64 n; + + __asm__ __volatile__ ( + "rdtime %0" + : "=r" (n)); + + return n; +#else + u32 lo, hi, tmp; + + __asm__ __volatile__ ( + "1:\n" + "rdtimeh %0\n" + "rdtime %1\n" + "rdtimeh %2\n" + "bne %0, %2, 1b" + : "=&r" (hi), "=&r" (lo), "=&r" (tmp)); + + return ((u64)hi << 32) | lo; +#endif +}