From patchwork Fri Dec 7 13:50:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 1009441 X-Patchwork-Delegate: hs@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="J22PvnLQ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43BDjy3WYNz9rxp for ; Sat, 8 Dec 2018 01:04:38 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 14C2FC22707; Fri, 7 Dec 2018 13:57:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 336AFC22707; Fri, 7 Dec 2018 13:51:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AF53AC2273E; Fri, 7 Dec 2018 13:51:24 +0000 (UTC) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lists.denx.de (Postfix) with ESMTPS id 348D7C2271F for ; Fri, 7 Dec 2018 13:51:20 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wB7DpIMt094188; Fri, 7 Dec 2018 07:51:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1544190678; bh=yf6EliAy1XrSVzLtehvVCml4iSW4ICkALRpmFoNGMP8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=J22PvnLQ7gKo61QtBsXEbcmFTT0WmNsQLBfs05rIhCoFMwAlEProtgmRXej8GNbMo MOc30BxNtxw70sSWsRxn7GNAd3sWUnjYGJR1EZXjYrqdHCgHWjehcdU/81Ozr/W9Xc KSyzdbnVs9CXx8jQJCauHDMACY3CDLbsBHMK0dI8= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wB7DpIwd066951 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 7 Dec 2018 07:51:18 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Fri, 7 Dec 2018 07:51:18 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Fri, 7 Dec 2018 07:51:18 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wB7DpHux014593; Fri, 7 Dec 2018 07:51:18 -0600 From: Jean-Jacques Hiblot To: , Date: Fri, 7 Dec 2018 14:50:51 +0100 Message-ID: <1544190655-4405-16-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544190655-4405-1-git-send-email-jjhiblot@ti.com> References: <1544190655-4405-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [RESEND PATCH v3 15/19] configs: dra7xx-evm: increase the size of the malloc's pool before relocation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is required to take advantage of MULTI_DTB_FIT before relocation. If it is too low, DM will be initialized only after relocation has taken place. That is too late for the DRA7 because I2C DM is used before the relocation to setup the voltages required, among other things, to properly initialize the DRAM. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Tom Rini Reviewed-by: Heiko Schocher --- Changes in v3: None Changes in v2: None configs/dra7xx_evm_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 27f6b5d..a57dc07 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 CONFIG_OMAP54XX=y CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL=y