| Message ID | 1544176659-32022-1-git-send-email-Anson.Huang@nxp.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [1/3] dt-bindings: clock: imx7ulp: add HSRUN mode related clocks | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
Quoting Anson Huang (2018-12-07 02:03:29) > There are HSRUN mode clock mux and divider in SCG1 module, > and SMC1 can control i.MX7ULP CPU to run in RUN mode or > HSRUN mode, the mode switch bits are actually a clock mux, > add these clocks for clock driver and dtb to use. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- Applied to clk-next
Quoting Anson Huang (2018-12-07 02:03:34) > i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode > or HSRUN mode, it is controlled in SMC1 module. The RUN > mode and HSRUN mode will use different clock source for > ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN > mode, so the control bits in SMC1 module can be abstracted > as a HW clock mux, this patch adds HSRUN mode related > clocks in SCG1 module and adds "arm" clock in SMC1 module > to support RUN mode and HSRUN mode switch. > > Latest clock tree in RUN mode as below: > > firc 0 0 0 48000000 0 0 50000 > firc_bus_clk 0 0 0 48000000 0 0 50000 > hsrun_scs_sel 0 0 0 48000000 0 0 50000 > hsrun_divcore 0 0 0 48000000 0 0 50000 > > sosc 3 3 3 24000000 0 0 50000 > spll_pre_sel 1 1 1 24000000 0 0 50000 > spll_pre_div 1 1 2 24000000 0 0 50000 > spll 1 1 2 528000000 0 0 50000 > spll_pfd0 1 1 1 500210526 0 0 50000 > spll_pfd_sel 1 1 0 500210526 0 0 50000 > spll_sel 1 1 0 500210526 0 0 50000 > scs_sel 1 1 0 500210526 0 0 50000 > divcore 1 1 0 500210526 0 0 50000 > arm 1 1 0 500210526 0 0 50000 > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- Applied to clk-next
On Fri, Dec 07, 2018 at 10:03:39AM +0000, Anson Huang wrote: > i.MX7ULP can switch CPU between RUN mode and HSRUN mode > by programming SMC1 register, different clock sources > will be used for CPU in different modes, so SMC1 can be > abstracted as a clock controller for CPU clock switch, > this patch adds support for it. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Applied, thanks.
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 008c5ee..21d872e 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -54,8 +54,10 @@ #define IMX7ULP_CLK_SOSC_BUS_CLK 41 #define IMX7ULP_CLK_FIRC_BUS_CLK 42 #define IMX7ULP_CLK_SPLL_BUS_CLK 43 +#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 +#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 -#define IMX7ULP_CLK_SCG1_END 44 +#define IMX7ULP_CLK_SCG1_END 46 /* PCC2 */ #define IMX7ULP_CLK_DMA1 0 @@ -106,4 +108,9 @@ #define IMX7ULP_CLK_PCC3_END 16 +/* SMC1 */ +#define IMX7ULP_CLK_ARM 0 + +#define IMX7ULP_CLK_SMC1_END 1 + #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
There are HSRUN mode clock mux and divider in SCG1 module, and SMC1 can control i.MX7ULP CPU to run in RUN mode or HSRUN mode, the mode switch bits are actually a clock mux, add these clocks for clock driver and dtb to use. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- include/dt-bindings/clock/imx7ulp-clock.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)