[1/2] dt-bindings: Add Qualcomm USB Super-Speed PHY bindings

Message ID 1544176558-7946-2-git-send-email-jorge.ramirez-ortiz@linaro.org
State Changes Requested
Headers show
Series
  • USB SS PHY for Qualcomm's QCS404
Related show

Checks

Context Check Description
robh/checkpatch success

Commit Message

Jorge Ramirez-Ortiz Dec. 7, 2018, 9:55 a.m.
Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
controller embedded in QCS404.

Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
definitions.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
---
 .../devicetree/bindings/usb/qcom,usb-ssphy.txt     | 78 ++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt

Comments

Jorge Ramirez-Ortiz Dec. 20, 2018, 9:52 a.m. | #1
On 07/12/18 10:55:57, Jorge Ramirez-Ortiz wrote:
> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
> controller embedded in QCS404.
> 
> Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
> definitions.
> 
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>

any follow up on this patchset?

thanks
Rob Herring Dec. 20, 2018, 5:05 p.m. | #2
On Fri, Dec 07, 2018 at 10:55:57AM +0100, Jorge Ramirez-Ortiz wrote:
> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
> controller embedded in QCS404.
> 
> Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
> definitions.
> 
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> ---
>  .../devicetree/bindings/usb/qcom,usb-ssphy.txt     | 78 ++++++++++++++++++++++
>  1 file changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> 
> diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> new file mode 100644
> index 0000000..fcf4e01
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> @@ -0,0 +1,78 @@
> +Qualcomm Synopsys 1.0.0 SS phy controller
> +===========================================
> +
> +Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm
> +chipsets
> +
> +Required properties:
> +
> +- compatible:
> +    Value type: <string>
> +    Definition: Should contain "qcom,usb-ssphy".

What is "qcom,dwc3-ss-usb-phy" which already exists then?

> +
> +- reg:
> +    Value type: <prop-encoded-array>
> +    Definition: USB PHY base address and length of the register map.
> +
> +- #phy-cells:
> +    Value type: <u32>
> +    Definition: Should be 0. See phy/phy-bindings.txt for details.
> +
> +- clocks:
> +    Value type: <prop-encoded-array>
> +    Definition: See clock-bindings.txt section "consumers". List of
> +		 three clock specifiers for reference, phy core and
> +		 pipe clocks.
> +
> +- clock-names:
> +    Value type: <string>
> +    Definition: Names of the clocks in 1-1 correspondence with the "clocks"
> +		 property. Must contain "ref", "phy" and "pipe".
> +
> +- vdd-supply:
> +    Value type: <phandle>
> +    Definition: phandle to the regulator VDD supply node.
> +
> +- vdda1p8-supply:
> +    Value type: <phandle>
> +    Definition: phandle to the regulator 1.8V supply node.
> +
> +- qcom,vdd-voltage-level:
> +    Value type: <prop-array>
> +    Definition: This is a list of three integer values <no min max> where
> +		 each value corresponding to voltage corner in uV.
> +
> +Optional child nodes:
> +
> +- vbus-supply:
> +    Value type: <phandle>
> +    Definition: phandle to the VBUS supply node.
> +
> +- resets:
> +    Value type: <prop-encoded-array>
> +    Definition: See reset.txt section "consumers". PHY reset specifiers
> +		 for phy core and COR resets.
> +
> +- reset-names:
> +    Value type: <string>
> +    Definition: Names of the resets in 1-1 correspondence with the "resets"
> +		 property. Must contain "com" and "phy".
> +
> +Example:
> +
> +usb3_phy: phy@78000 {
> +	compatible = "qcom,usb-ssphy";
> +	reg = <0x78000 0x400>;
> +	#phy-cells = <0>;
> +	clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
> +		 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
> +		 <&gcc GCC_USB3_PHY_PIPE_CLK>;
> +	clock-names = "ref", "phy", "pipe";
> +	resets = <&gcc GCC_USB3_PHY_BCR>,
> +		 <&gcc GCC_USB3PHY_PHY_BCR>;
> +	reset-names = "com", "phy";
> +	vdd-supply = <&vreg_l3_1p05>;
> +	vdda1p8-supply = <&vreg_l5_1p8>;
> +	vbus-supply = <&usb3_vbus_reg>;
> +	qcom,vdd-voltage-level = <0 1050000 1050000>;
> +};
> -- 
> 2.7.4
>
Rob Herring Dec. 20, 2018, 5:07 p.m. | #3
On Thu, Dec 20, 2018 at 10:52:45AM +0100, Jorge Ramirez-Ortiz wrote:
> On 07/12/18 10:55:57, Jorge Ramirez-Ortiz wrote:
> > Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
> > controller embedded in QCS404.
> > 
> > Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
> > definitions.
> > 
> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> > Reviewed-by: Vinod Koul <vkoul@kernel.org>
> 
> any follow up on this patchset?

Check DT patchwork[1] if you want to know where you are in the queue. 
Just so happened to get to it now.

Rob

[1] https://patchwork.ozlabs.org/project/devicetree-bindings/list/
Jack Pham Dec. 20, 2018, 5:37 p.m. | #4
Hi Rob, Jorge,

On Thu, Dec 20, 2018 at 11:05:31AM -0600, Rob Herring wrote:
> On Fri, Dec 07, 2018 at 10:55:57AM +0100, Jorge Ramirez-Ortiz wrote:
> > Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
> > controller embedded in QCS404.
> > 
> > Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
> > definitions.
> > 
> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> > Reviewed-by: Vinod Koul <vkoul@kernel.org>
> > ---
> >  .../devicetree/bindings/usb/qcom,usb-ssphy.txt     | 78 ++++++++++++++++++++++
> >  1 file changed, 78 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> > new file mode 100644
> > index 0000000..fcf4e01
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> > @@ -0,0 +1,78 @@
> > +Qualcomm Synopsys 1.0.0 SS phy controller
> > +===========================================
> > +
> > +Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm
> > +chipsets
> > +
> > +Required properties:
> > +
> > +- compatible:
> > +    Value type: <string>
> > +    Definition: Should contain "qcom,usb-ssphy".
> 
> What is "qcom,dwc3-ss-usb-phy" which already exists then?

Uh, apparently only the bindings doc is there but the driver never
landed. I guess it fell through the cracks nearly 4 years ago.

https://lore.kernel.org/patchwork/patch/499502/

Jorge, does Andy's version of this driver at all resemble what can be
used for QCS404?

Jack
Stephen Boyd Dec. 20, 2018, 8:25 p.m. | #5
Quoting Jorge Ramirez-Ortiz (2018-12-07 01:55:57)
> +
> +- qcom,vdd-voltage-level:
> +    Value type: <prop-array>
> +    Definition: This is a list of three integer values <no min max> where
> +                each value corresponding to voltage corner in uV.

As far as I'm aware, this isn't how qcom's voltage corners are handled
or are going to be handled. Can't you hardcode it in the driver for now?
Jorge Ramirez-Ortiz Dec. 21, 2018, 7:37 a.m. | #6
On 12/20/18 21:25, Stephen Boyd wrote:
> Quoting Jorge Ramirez-Ortiz (2018-12-07 01:55:57)
>> +
>> +- qcom,vdd-voltage-level:
>> +    Value type: <prop-array>
>> +    Definition: This is a list of three integer values <no min max> where
>> +                each value corresponding to voltage corner in uV.
> As far as I'm aware, this isn't how qcom's voltage corners are handled
> or are going to be handled. Can't you hardcode it in the driver for now?
>
>

ok so you mean use a regulator to control the supply (with 
regulator-min-microvolt and max-microvolt properties instead?
I'll look into that

I guess we should pull back on this one as well?
https://lore.kernel.org/patchwork/patch/1026641/
Jorge Ramirez-Ortiz Dec. 21, 2018, 7:40 a.m. | #7
On 12/20/18 18:37, Jack Pham wrote:
> Hi Rob, Jorge,
>
> On Thu, Dec 20, 2018 at 11:05:31AM -0600, Rob Herring wrote:
>> On Fri, Dec 07, 2018 at 10:55:57AM +0100, Jorge Ramirez-Ortiz wrote:
>>> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
>>> controller embedded in QCS404.
>>>
>>> Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
>>> definitions.
>>>
>>> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
>>> Reviewed-by: Vinod Koul <vkoul@kernel.org>
>>> ---
>>>   .../devicetree/bindings/usb/qcom,usb-ssphy.txt     | 78 ++++++++++++++++++++++
>>>   1 file changed, 78 insertions(+)
>>>   create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
>>> new file mode 100644
>>> index 0000000..fcf4e01
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
>>> @@ -0,0 +1,78 @@
>>> +Qualcomm Synopsys 1.0.0 SS phy controller
>>> +===========================================
>>> +
>>> +Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm
>>> +chipsets
>>> +
>>> +Required properties:
>>> +
>>> +- compatible:
>>> +    Value type: <string>
>>> +    Definition: Should contain "qcom,usb-ssphy".
>> What is "qcom,dwc3-ss-usb-phy" which already exists then?
> Uh, apparently only the bindings doc is there but the driver never
> landed. I guess it fell through the cracks nearly 4 years ago.
>
> https://lore.kernel.org/patchwork/patch/499502/
>
> Jorge, does Andy's version of this driver at all resemble what can be
> used for QCS404?

the drivers seem quite different but I'll give it a go as well and 
compare (it is my understanding that the controller is the same - I will 
have access to the hardware documentation soon to compare)

but I'll come back to you on this.

>
> Jack
Jorge Ramirez-Ortiz Dec. 21, 2018, 7:42 a.m. | #8
On 12/20/18 18:07, Rob Herring wrote:
> On Thu, Dec 20, 2018 at 10:52:45AM +0100, Jorge Ramirez-Ortiz wrote:
>> On 07/12/18 10:55:57, Jorge Ramirez-Ortiz wrote:
>>> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
>>> controller embedded in QCS404.
>>>
>>> Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
>>> definitions.
>>>
>>> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
>>> Reviewed-by: Vinod Koul <vkoul@kernel.org>
>> any follow up on this patchset?
> Check DT patchwork[1] if you want to know where you are in the queue.
> Just so happened to get to it now.

thanks for the info Rob. I honestly didnt know it operated in order! my 
fault

>
> Rob
>
> [1] https://patchwork.ozlabs.org/project/devicetree-bindings/list/
>
Jorge Ramirez-Ortiz Dec. 26, 2018, 5:55 p.m. | #9
On 12/20/18 21:25, Stephen Boyd wrote:
> Quoting Jorge Ramirez-Ortiz (2018-12-07 01:55:57)
>> +
>> +- qcom,vdd-voltage-level:
>> +    Value type: <prop-array>
>> +    Definition: This is a list of three integer values <no min max> where
>> +                each value corresponding to voltage corner in uV.
> 
> As far as I'm aware, this isn't how qcom's voltage corners are handled
> or are going to be handled. Can't you hardcode it in the driver for now?
> 
> 

sure will do.

if there is any other driver in some tree/branch that I could be looking 
as a reference - to avoid having to hardcode the values in the driver- 
please let me know.
Jorge Ramirez-Ortiz Dec. 28, 2018, 12:38 p.m. | #10
On 12/20/18 18:37, Jack Pham wrote:
> Hi Rob, Jorge,
> 
> On Thu, Dec 20, 2018 at 11:05:31AM -0600, Rob Herring wrote:
>> On Fri, Dec 07, 2018 at 10:55:57AM +0100, Jorge Ramirez-Ortiz wrote:
>>> Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
>>> controller embedded in QCS404.
>>>
>>> Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
>>> definitions.
>>>
>>> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
>>> Reviewed-by: Vinod Koul <vkoul@kernel.org>
>>> ---
>>>   .../devicetree/bindings/usb/qcom,usb-ssphy.txt     | 78 ++++++++++++++++++++++
>>>   1 file changed, 78 insertions(+)
>>>   create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
>>> new file mode 100644
>>> index 0000000..fcf4e01
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
>>> @@ -0,0 +1,78 @@
>>> +Qualcomm Synopsys 1.0.0 SS phy controller
>>> +===========================================
>>> +
>>> +Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm
>>> +chipsets
>>> +
>>> +Required properties:
>>> +
>>> +- compatible:
>>> +    Value type: <string>
>>> +    Definition: Should contain "qcom,usb-ssphy".
>>
>> What is "qcom,dwc3-ss-usb-phy" which already exists then?
> 
> Uh, apparently only the bindings doc is there but the driver never
> landed. I guess it fell through the cracks nearly 4 years ago.
> 
> https://lore.kernel.org/patchwork/patch/499502/
> 
> Jorge, does Andy's version of this driver at all resemble what can be
> used for QCS404?

on close inspection I cant see any similitudes between the drivers. 
Unfortunately I don't have access to documentation yet but the control 
register offsets and the control bits in the drivers do not match.

because of the above I'd like to go ahead with our separate drivers 
-already tested and validated- for HS (Shawn's) and SS (mine).

if that is acceptable, should we reuse the upstream bindings for  our 
implementation? or perhaps Shawn Guo will do for his HS version of the 
driver and I go ahead and create a new one? what would you suggest?





> 
> Jack
>
Jack Pham Jan. 7, 2019, 8:26 p.m. | #11
Hi Jorge,

Sorry for the late reply as I was out during the holiday break.

On Fri, Dec 28, 2018 at 01:38:59PM +0100, Jorge Ramirez wrote:
> On 12/20/18 18:37, Jack Pham wrote:
> >Hi Rob, Jorge,
> >
> >On Thu, Dec 20, 2018 at 11:05:31AM -0600, Rob Herring wrote:
> >>On Fri, Dec 07, 2018 at 10:55:57AM +0100, Jorge Ramirez-Ortiz wrote:
> >>>Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
> >>>controller embedded in QCS404.
> >>>
> >>>Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
> >>>definitions.
> >>>
> >>>Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> >>>Reviewed-by: Vinod Koul <vkoul@kernel.org>
> >>>---
> >>>  .../devicetree/bindings/usb/qcom,usb-ssphy.txt     | 78 ++++++++++++++++++++++
> >>>  1 file changed, 78 insertions(+)
> >>>  create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> >>>
> >>>diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> >>>new file mode 100644
> >>>index 0000000..fcf4e01
> >>>--- /dev/null
> >>>+++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> >>>@@ -0,0 +1,78 @@
> >>>+Qualcomm Synopsys 1.0.0 SS phy controller
> >>>+===========================================
> >>>+
> >>>+Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm
> >>>+chipsets
> >>>+
> >>>+Required properties:
> >>>+
> >>>+- compatible:
> >>>+    Value type: <string>
> >>>+    Definition: Should contain "qcom,usb-ssphy".
> >>
> >>What is "qcom,dwc3-ss-usb-phy" which already exists then?
> >
> >Uh, apparently only the bindings doc is there but the driver never
> >landed. I guess it fell through the cracks nearly 4 years ago.
> >
> >https://lore.kernel.org/patchwork/patch/499502/
> >
> >Jorge, does Andy's version of this driver at all resemble what can be
> >used for QCS404?
> 
> on close inspection I cant see any similitudes between the drivers.
> Unfortunately I don't have access to documentation yet but the
> control register offsets and the control bits in the drivers do not
> match.
> 
> because of the above I'd like to go ahead with our separate drivers
> -already tested and validated- for HS (Shawn's) and SS (mine).
> 
> if that is acceptable, should we reuse the upstream bindings for
> our implementation? or perhaps Shawn Guo will do for his HS version
> of the driver and I go ahead and create a new one? what would you
> suggest?

I'm not really sure. My understanding of the driver Andy submitted
were for some of the older MSM and IPQ SoCs that implemented the PHY
controls as part of the DWC3 controller's "QScratch" registers, which is
why the bindings doc and the compatible string reference "dwc3" in both
the compatible and the docs filename. Is the SNPS PHY on QCS404
architected similarly in this regard? Either way, the existing bindings
doc for the non-existent driver looks incomplete for QCS404, so you'd
have to update it anyway. My feeling is that there should just be one
document describing all variants of SNPS PHYs on Qualcomm chips.

Maybe we should also just delete the "qcom,dwc3-ss-usb-phy" binding
unless there is a plan to resurrect Andy's driver.

Jack
Andy Gross Jan. 7, 2019, 8:33 p.m. | #12
On Mon, 7 Jan 2019 at 14:26, Jack Pham <jackp@codeaurora.org> wrote:
>
> Hi Jorge,
>
> Sorry for the late reply as I was out during the holiday break.
>
> On Fri, Dec 28, 2018 at 01:38:59PM +0100, Jorge Ramirez wrote:
> > On 12/20/18 18:37, Jack Pham wrote:
> > >Hi Rob, Jorge,
> > >
> > >On Thu, Dec 20, 2018 at 11:05:31AM -0600, Rob Herring wrote:
> > >>On Fri, Dec 07, 2018 at 10:55:57AM +0100, Jorge Ramirez-Ortiz wrote:
> > >>>Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY
> > >>>controller embedded in QCS404.
> > >>>
> > >>>Based on Sriharsha Allenki's <sallenki@codeaurora.org> original
> > >>>definitions.
> > >>>
> > >>>Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> > >>>Reviewed-by: Vinod Koul <vkoul@kernel.org>
> > >>>---
> > >>>  .../devicetree/bindings/usb/qcom,usb-ssphy.txt     | 78 ++++++++++++++++++++++
> > >>>  1 file changed, 78 insertions(+)
> > >>>  create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> > >>>
> > >>>diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> > >>>new file mode 100644
> > >>>index 0000000..fcf4e01
> > >>>--- /dev/null
> > >>>+++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
> > >>>@@ -0,0 +1,78 @@
> > >>>+Qualcomm Synopsys 1.0.0 SS phy controller
> > >>>+===========================================
> > >>>+
> > >>>+Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm
> > >>>+chipsets
> > >>>+
> > >>>+Required properties:
> > >>>+
> > >>>+- compatible:
> > >>>+    Value type: <string>
> > >>>+    Definition: Should contain "qcom,usb-ssphy".
> > >>
> > >>What is "qcom,dwc3-ss-usb-phy" which already exists then?
> > >
> > >Uh, apparently only the bindings doc is there but the driver never
> > >landed. I guess it fell through the cracks nearly 4 years ago.
> > >
> > >https://lore.kernel.org/patchwork/patch/499502/
> > >
> > >Jorge, does Andy's version of this driver at all resemble what can be
> > >used for QCS404?
> >
> > on close inspection I cant see any similitudes between the drivers.
> > Unfortunately I don't have access to documentation yet but the
> > control register offsets and the control bits in the drivers do not
> > match.
> >
> > because of the above I'd like to go ahead with our separate drivers
> > -already tested and validated- for HS (Shawn's) and SS (mine).
> >
> > if that is acceptable, should we reuse the upstream bindings for
> > our implementation? or perhaps Shawn Guo will do for his HS version
> > of the driver and I go ahead and create a new one? what would you
> > suggest?
>
> I'm not really sure. My understanding of the driver Andy submitted
> were for some of the older MSM and IPQ SoCs that implemented the PHY
> controls as part of the DWC3 controller's "QScratch" registers, which is
> why the bindings doc and the compatible string reference "dwc3" in both
> the compatible and the docs filename. Is the SNPS PHY on QCS404
> architected similarly in this regard? Either way, the existing bindings
> doc for the non-existent driver looks incomplete for QCS404, so you'd
> have to update it anyway. My feeling is that there should just be one
> document describing all variants of SNPS PHYs on Qualcomm chips.

Yeah the original driver was specifically for the IPQ8064 phys.  The
actual phy driver changed over time
due to some comments from a few people, but it still used the qscratch
memory for the phy control regs.

Due to this never landing, you can change the phy binding to work for
both of them or just for yours.  If the control
regs are totally different for the QCS404 phy, it should use a
different compatible and driver.  That's my 2 cents.


> Maybe we should also just delete the "qcom,dwc3-ss-usb-phy" binding
> unless there is a plan to resurrect Andy's driver.

I have the hardware I just don't have the time in the short-mid term
to resurrect this.  Unless someone else
wants to pick this up, it'll be a while.  In the meantime, I'd suggest
just changing the binding to apply to the QCS404
if that makes sense (completely different IP / register layout).

Andy

Patch

diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
new file mode 100644
index 0000000..fcf4e01
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt
@@ -0,0 +1,78 @@ 
+Qualcomm Synopsys 1.0.0 SS phy controller
+===========================================
+
+Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm
+chipsets
+
+Required properties:
+
+- compatible:
+    Value type: <string>
+    Definition: Should contain "qcom,usb-ssphy".
+
+- reg:
+    Value type: <prop-encoded-array>
+    Definition: USB PHY base address and length of the register map.
+
+- #phy-cells:
+    Value type: <u32>
+    Definition: Should be 0. See phy/phy-bindings.txt for details.
+
+- clocks:
+    Value type: <prop-encoded-array>
+    Definition: See clock-bindings.txt section "consumers". List of
+		 three clock specifiers for reference, phy core and
+		 pipe clocks.
+
+- clock-names:
+    Value type: <string>
+    Definition: Names of the clocks in 1-1 correspondence with the "clocks"
+		 property. Must contain "ref", "phy" and "pipe".
+
+- vdd-supply:
+    Value type: <phandle>
+    Definition: phandle to the regulator VDD supply node.
+
+- vdda1p8-supply:
+    Value type: <phandle>
+    Definition: phandle to the regulator 1.8V supply node.
+
+- qcom,vdd-voltage-level:
+    Value type: <prop-array>
+    Definition: This is a list of three integer values <no min max> where
+		 each value corresponding to voltage corner in uV.
+
+Optional child nodes:
+
+- vbus-supply:
+    Value type: <phandle>
+    Definition: phandle to the VBUS supply node.
+
+- resets:
+    Value type: <prop-encoded-array>
+    Definition: See reset.txt section "consumers". PHY reset specifiers
+		 for phy core and COR resets.
+
+- reset-names:
+    Value type: <string>
+    Definition: Names of the resets in 1-1 correspondence with the "resets"
+		 property. Must contain "com" and "phy".
+
+Example:
+
+usb3_phy: phy@78000 {
+	compatible = "qcom,usb-ssphy";
+	reg = <0x78000 0x400>;
+	#phy-cells = <0>;
+	clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+		 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+		 <&gcc GCC_USB3_PHY_PIPE_CLK>;
+	clock-names = "ref", "phy", "pipe";
+	resets = <&gcc GCC_USB3_PHY_BCR>,
+		 <&gcc GCC_USB3PHY_PHY_BCR>;
+	reset-names = "com", "phy";
+	vdd-supply = <&vreg_l3_1p05>;
+	vdda1p8-supply = <&vreg_l5_1p8>;
+	vbus-supply = <&usb3_vbus_reg>;
+	qcom,vdd-voltage-level = <0 1050000 1050000>;
+};