From patchwork Fri Dec 7 09:19:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harald Seiler X-Patchwork-Id: 1009252 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43B6PM4jx3z9s3q for ; Fri, 7 Dec 2018 20:19:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B040BC226D0; Fri, 7 Dec 2018 09:19:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 982C5C21E6C; Fri, 7 Dec 2018 09:19:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7AE06C21E6C; Fri, 7 Dec 2018 09:19:38 +0000 (UTC) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by lists.denx.de (Postfix) with ESMTPS id 2D721C21E56 for ; Fri, 7 Dec 2018 09:19:38 +0000 (UTC) Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 43B6P56zllz1r2n9; Fri, 7 Dec 2018 10:19:37 +0100 (CET) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 43B6P56dPzz1qtfF; Fri, 7 Dec 2018 10:19:37 +0100 (CET) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id VyIhjAu-x0Wr; Fri, 7 Dec 2018 10:19:37 +0100 (CET) X-Auth-Info: NHnZXnswiZGTVQP2hWNBbAyjXn3ROhx1tdMC6Gp4saU= Received: from elite.denx.de (p578adb1c.dip0.t-ipconnect.de [87.138.219.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Fri, 7 Dec 2018 10:19:37 +0100 (CET) Message-ID: <1544174376.2518.2.camel@denx.de> From: Harald Seiler To: U-Boot@lists.denx.de, Stefano Babic Date: Fri, 07 Dec 2018 10:19:36 +0100 In-Reply-To: <955e2a76-d21d-cec8-f3ce-f0e6613b52f6@denx.de> References: <955e2a76-d21d-cec8-f3ce-f0e6613b52f6@denx.de> X-Mailer: Evolution 3.26.6 (3.26.6-1.fc27) Mime-Version: 1.0 Cc: Marek Vasut Subject: [U-Boot] [PATCH v2] pcm058: fix NAND flash not using badblock table X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently, U-Boot ignores the BBT stored in the last 4 blocks of NAND flash because the NAND_BBT_USE_FLASH flag is not set. This leads to two issues: * U-Boot silently uses a memory-only BBT which is initialized with all blocks marked as good. This means, actual bad blocks are marked good and U-Boot might try writing to or reading from them. * The BBT in flash, which will be created once Linux boots up, is not off limits for a driver ontop, like UBI. While it does not seem to consistently produce an error, sometimes UBI will fail to attach because the BBT blocks obviously don't contain valid UBI data. To fix this, this patch sets the CONFIG_SYS_NAND_USE_FLASH_BBT option, which is used in ./drivers/mtd/nand/raw/mxs_nand.c to decide whether a BBT in flash is used. Signed-off-by: Harald Seiler --- include/configs/pcm058.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 49048c163f..b9bc08b388 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -55,6 +55,7 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT #endif /* DMA stuff, needed for GPMI/MXS NAND support */