From patchwork Fri Jun 17 20:39:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 100860 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0DC7DB6FD2 for ; Sat, 18 Jun 2011 07:04:33 +1000 (EST) Received: from localhost ([::1]:51042 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QXgDN-0003Qe-NU for incoming@patchwork.ozlabs.org; Fri, 17 Jun 2011 17:04:29 -0400 Received: from eggs.gnu.org ([140.186.70.92]:41191) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QXfpK-0005cw-OF for qemu-devel@nongnu.org; Fri, 17 Jun 2011 16:39:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QXfpI-0005vT-9P for qemu-devel@nongnu.org; Fri, 17 Jun 2011 16:39:38 -0400 Received: from db3ehsobe001.messaging.microsoft.com ([213.199.154.139]:41472 helo=DB3EHSOBE001.bigfish.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QXfpH-0005vA-Hy for qemu-devel@nongnu.org; Fri, 17 Jun 2011 16:39:35 -0400 Received: from mail112-db3-R.bigfish.com (10.3.81.248) by DB3EHSOBE001.bigfish.com (10.3.84.21) with Microsoft SMTP Server id 14.1.225.22; Fri, 17 Jun 2011 20:39:34 +0000 Received: from mail112-db3 (localhost.localdomain [127.0.0.1]) by mail112-db3-R.bigfish.com (Postfix) with ESMTP id 0EF12121839B; Fri, 17 Jun 2011 20:39:34 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h62h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail112-db3 (localhost.localdomain [127.0.0.1]) by mail112-db3 (MessageSwitch) id 1308343172621125_22764; Fri, 17 Jun 2011 20:39:32 +0000 (UTC) Received: from DB3EHSMHS001.bigfish.com (unknown [10.3.81.240]) by mail112-db3.bigfish.com (Postfix) with ESMTP id 94D8D790053; Fri, 17 Jun 2011 20:39:32 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS001.bigfish.com (10.3.87.101) with Microsoft SMTP Server (TLS) id 14.1.225.22; Fri, 17 Jun 2011 20:39:32 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.289.8; Fri, 17 Jun 2011 15:39:30 -0500 Received: from schlenkerla.am.freescale.net (schlenkerla.am.freescale.net [10.82.121.12]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p5HKdU6U010044; Fri, 17 Jun 2011 15:39:30 -0500 (CDT) Date: Fri, 17 Jun 2011 15:39:30 -0500 From: Scott Wood To: Message-ID: <20110617203929.GA16894@schlenkerla.am.freescale.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20110617203844.GA16832@schlenkerla.am.freescale.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows 2000 SP2+, XP SP1+ (seldom 98) X-Received-From: 213.199.154.139 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 1/3] kvm: ppc: booke206: use MMU API X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Share the TLB array with KVM. This allows us to set the initial TLB both on initial boot and reset, is useful for debugging, and could eventually be used to support migration. Signed-off-by: Scott Wood --- hw/ppce500_mpc8544ds.c | 2 + target-ppc/cpu.h | 2 + target-ppc/kvm.c | 85 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 0 deletions(-) diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index 5ac8843..3cdeb43 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -192,6 +192,8 @@ static void mmubooke_create_initial_mapping(CPUState *env, tlb->mas2 = va & TARGET_PAGE_MASK; tlb->mas7_3 = pa & TARGET_PAGE_MASK; tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; + + env->tlb_dirty = true; } static void mpc8544ds_cpu_reset(void *opaque) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 46d86be..8191ed2 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -921,6 +921,8 @@ struct CPUPPCState { ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ /* 403 dedicated access protection registers */ target_ulong pb[4]; + bool tlb_dirty; /* Set to non-zero when modifying TLB */ + bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ #endif /* Other registers */ diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index e7b1b10..9a88fc9 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -122,6 +122,51 @@ static int kvm_arch_sync_sregs(CPUState *cenv) return kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); } +static int kvm_booke206_tlb_init(CPUState *env) +{ +#if defined(KVM_CAP_SW_TLB) && defined(KVM_MMU_FSL_BOOKE_NOHV) + struct kvm_book3e_206_tlb_params params = {}; + struct kvm_config_tlb cfg = {}; + size_t array_len; + unsigned int entries = 0; + int ret, i; + + if (!kvm_enabled() || + !kvm_check_extension(env->kvm_state, KVM_CAP_SW_TLB)) { + return 0; + } + + for (i = 0; i < ARRAY_SIZE(params.tlb_sizes); i++) { + params.tlb_sizes[i] = booke206_tlb_size(env, i); + params.tlb_ways[i] = booke206_tlb_ways(env, i); + entries += params.tlb_sizes[i]; + } + + if (entries != env->nb_tlb) { + cpu_abort(env, "%s: nb_tlb mismatch\n", __func__); + } + + array_len = sizeof(struct kvm_book3e_206_tlb_entry) * entries; + env->tlb_dirty = true; + + cfg.array = (uintptr_t)env->tlb.tlbm; + cfg.array_len = sizeof(ppcmas_tlb_t) * entries; + cfg.params = (uintptr_t)¶ms; + cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; + + ret = kvm_vcpu_ioctl(env, KVM_CONFIG_TLB, &cfg); + if (ret < 0) { + fprintf(stderr, "%s: couldn't KVM_CONFIG_TLB: %s\n", + __func__, strerror(-ret)); + return ret; + } + + env->kvm_sw_tlb = true; +#endif + + return 0; +} + int kvm_arch_init_vcpu(CPUState *cenv) { int ret; @@ -133,6 +178,14 @@ int kvm_arch_init_vcpu(CPUState *cenv) idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv); + switch (cenv->mmu_model) { + case POWERPC_MMU_BOOKE206: + ret = kvm_booke206_tlb_init(cenv); + break; + default: + break; + } + return ret; } @@ -140,6 +193,33 @@ void kvm_arch_reset_vcpu(CPUState *env) { } +static void kvm_sw_tlb_put(CPUState *env) +{ +#if defined(KVM_CAP_SW_TLB) + struct kvm_dirty_tlb dirty_tlb; + unsigned char *bitmap; + int ret; + + if (!env->kvm_sw_tlb) { + return; + } + + bitmap = qemu_malloc((env->nb_tlb + 7) / 8); + memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); + + dirty_tlb.bitmap = (uintptr_t)bitmap; + dirty_tlb.num_dirty = env->nb_tlb; + + ret = kvm_vcpu_ioctl(env, KVM_DIRTY_TLB, &dirty_tlb); + if (ret) { + fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", + __func__, strerror(-ret)); + } + + qemu_free(bitmap); +#endif +} + int kvm_arch_put_registers(CPUState *env, int level) { struct kvm_regs regs; @@ -177,6 +257,11 @@ int kvm_arch_put_registers(CPUState *env, int level) if (ret < 0) return ret; + if (env->tlb_dirty) { + kvm_sw_tlb_put(env); + env->tlb_dirty = false; + } + return ret; }