From patchwork Thu Dec 6 00:02:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1008548 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 439G6s5K0Cz9rxp for ; Thu, 6 Dec 2018 11:04:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 753DFC22039; Thu, 6 Dec 2018 00:04:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 95B34C21E7D; Thu, 6 Dec 2018 00:03:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7382EC21E7D; Thu, 6 Dec 2018 00:03:24 +0000 (UTC) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id 2A2DFC21DFB for ; Thu, 6 Dec 2018 00:03:20 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 297A780D; Wed, 5 Dec 2018 16:03:19 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DAC203F614; Wed, 5 Dec 2018 16:03:17 -0800 (PST) From: Andre Przywara To: Maxime Ripard , Jagan Teki Date: Thu, 6 Dec 2018 00:02:20 +0000 Message-Id: <20181206000220.2302-1-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 Cc: u-boot@lists.denx.de, Jernej Skrabec , Icenowy Zheng Subject: [U-Boot] [PATCH] sunxi: H6: DRAM: avoid memcpy() on MMIO registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Using memcpy() for MMIO operations is, however tempting, not a good idea: It depends on the specific implementation of memcpy, also lacks barriers. In this particular case the first registers were written using 64-bit writes, and the last register using four separate single-byte writes. Neither is what we actually want. We get away with it in this case because of the particular details of the bus implementation, the DRAM controller IP and the values that we actually write, but we should not leave a bad example around. Replace the memcpy with a proper loop using the writel() accessor. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/dram_sun50i_h6.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 5da90a2835..e2f141eb9b 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -182,6 +182,7 @@ static void mctl_set_timing_lpddr3(struct dram_para *para) (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; struct sunxi_mctl_phy_reg * const mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + int i; u8 tccd = 2; u8 tfaw = max(ns_to_t(50), 4); @@ -237,8 +238,9 @@ static void mctl_set_timing_lpddr3(struct dram_para *para) u8 twr2rd = tcwl + 4 + 1 + twtr; u8 trd2wr = tcl + 4 + (tcksrea >> 1) - tcwl + 1; - /* set mode register */ - memcpy(mctl_phy->mr, mr_lpddr3, sizeof(mr_lpddr3)); + /* set mode registers */ + for (i = 0; i < ARRAY_SIZE(mr_lpddr3); i++) + writel(mr_lpddr3[i], &mctl_phy->mr[i]); /* set DRAM timing */ writel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,