From patchwork Wed Dec 5 17:10:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 1008353 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4394yr0gLWz9s7W for ; Thu, 6 Dec 2018 04:11:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A4872C22641; Wed, 5 Dec 2018 17:11:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A26E8C22462; Wed, 5 Dec 2018 17:11:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F1D64C21F52; Wed, 5 Dec 2018 17:11:03 +0000 (UTC) Received: from mail.bootlin.com (mail.bootlin.com [62.4.15.54]) by lists.denx.de (Postfix) with ESMTP id 7D49FC21F82 for ; Wed, 5 Dec 2018 17:11:03 +0000 (UTC) Received: by mail.bootlin.com (Postfix, from userid 110) id C7BA120A63; Wed, 5 Dec 2018 18:11:02 +0100 (CET) Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.bootlin.com (Postfix) with ESMTPSA id 9D8D220729; Wed, 5 Dec 2018 18:11:02 +0100 (CET) From: Gregory CLEMENT To: Daniel Schwierzeck Date: Wed, 5 Dec 2018 18:10:49 +0100 Message-Id: <20181205171054.926-3-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205171054.926-1-gregory.clement@bootlin.com> References: <20181205171054.926-1-gregory.clement@bootlin.com> MIME-Version: 1.0 Cc: Antoine Tenart , Steen.Hegelund@microchip.com, u-boot@lists.denx.de, Allan Nielsen , Thomas Petazzoni , =?utf-8?b?TWlxdcOo?= =?utf-8?q?l_Raynal?= Subject: [U-Boot] [PATCH v3 2/7] MIPS: Allow to prefetch and lock instructions into cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This path add a new helper allowing to prefetch and lock instructions into cache. This is useful very early in the boot when no RAM is available yet. Signed-off-by: Gregory CLEMENT --- arch/mips/include/asm/cacheops.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 3161875441..98b67ccc8e 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void *addr) #endif } +#define MIPS32_WHICH_ICACHE 0x0 +#define MIPS32_FETCH_AND_LOCK 0x7 + +#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2)) + +/* Prefetch and lock instructions into cache */ +static inline void icache_lock(void *func, size_t len) +{ + int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1; + + for (i = 0; i < lines; i++) { + asm volatile (" cache %0, %1(%2)" + : /* No Output */ + : "I" ICACHE_LOAD_LOCK, + "n" (i * ARCH_DMA_MINALIGN), + "r" (func) + : /* No Clobbers */); + } +} #endif /* !__ASSEMBLY__ */ /*