| Message ID | 20181205062924.26640-3-anup@brainfault.org |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | SiFive UART support | expand |
On Tue, 04 Dec 2018 22:29:24 PST (-0800), anup@brainfault.org wrote: > This patch enables SiFive UART driver in all QEMU RISC-V defconfigs. > > Signed-off-by: Anup Patel <anup@brainfault.org> > --- > configs/qemu-riscv32_defconfig | 1 + > configs/qemu-riscv32_smode_defconfig | 1 + > configs/qemu-riscv64_defconfig | 1 + > configs/qemu-riscv64_smode_defconfig | 1 + > 4 files changed, 4 insertions(+) > > diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig > index 6334d8c0fc..79c8d54cc7 100644 > --- a/configs/qemu-riscv32_defconfig > +++ b/configs/qemu-riscv32_defconfig > @@ -7,3 +7,4 @@ CONFIG_DISPLAY_CPUINFO=y > CONFIG_DISPLAY_BOARDINFO=y > # CONFIG_CMD_MII is not set > CONFIG_OF_PRIOR_STAGE=y > +CONFIG_SIFIVE_SERIAL=y > diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig > index 0a84ec1874..b733dbed2f 100644 > --- a/configs/qemu-riscv32_smode_defconfig > +++ b/configs/qemu-riscv32_smode_defconfig > @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y > CONFIG_DISPLAY_BOARDINFO=y > # CONFIG_CMD_MII is not set > CONFIG_OF_PRIOR_STAGE=y > +CONFIG_SIFIVE_SERIAL=y > diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig > index 2d9ead93a2..a9d19a5574 100644 > --- a/configs/qemu-riscv64_defconfig > +++ b/configs/qemu-riscv64_defconfig > @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y > CONFIG_DISPLAY_BOARDINFO=y > # CONFIG_CMD_MII is not set > CONFIG_OF_PRIOR_STAGE=y > +CONFIG_SIFIVE_SERIAL=y > diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig > index b012443370..8adc23f826 100644 > --- a/configs/qemu-riscv64_smode_defconfig > +++ b/configs/qemu-riscv64_smode_defconfig > @@ -9,3 +9,4 @@ CONFIG_DISPLAY_CPUINFO=y > CONFIG_DISPLAY_BOARDINFO=y > # CONFIG_CMD_MII is not set > CONFIG_OF_PRIOR_STAGE=y > +CONFIG_SIFIVE_SERIAL=y Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Hi Anup, On Wed, Dec 5, 2018 at 2:29 PM Anup Patel <anup@brainfault.org> wrote: > > This patch enables SiFive UART driver in all QEMU RISC-V defconfigs. > > Signed-off-by: Anup Patel <anup@brainfault.org> > --- > configs/qemu-riscv32_defconfig | 1 + > configs/qemu-riscv32_smode_defconfig | 1 + > configs/qemu-riscv64_defconfig | 1 + > configs/qemu-riscv64_smode_defconfig | 1 + > 4 files changed, 4 insertions(+) > Can we "imply SIFIVE_SERIAL" in BOARD_SPECIFIC_OPTIONS in board/emulation/qemu-riscv/Kconfig instead? [snip] Regards, Bin
On Mon, Dec 10, 2018 at 7:25 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Anup, > > On Wed, Dec 5, 2018 at 2:29 PM Anup Patel <anup@brainfault.org> wrote: > > > > This patch enables SiFive UART driver in all QEMU RISC-V defconfigs. > > > > Signed-off-by: Anup Patel <anup@brainfault.org> > > --- > > configs/qemu-riscv32_defconfig | 1 + > > configs/qemu-riscv32_smode_defconfig | 1 + > > configs/qemu-riscv64_defconfig | 1 + > > configs/qemu-riscv64_smode_defconfig | 1 + > > 4 files changed, 4 insertions(+) > > > > Can we "imply SIFIVE_SERIAL" in BOARD_SPECIFIC_OPTIONS in > board/emulation/qemu-riscv/Kconfig instead? Sure, will do. If it works then I will drop this patch. Regards, Anup
diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 6334d8c0fc..79c8d54cc7 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -7,3 +7,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 0a84ec1874..b733dbed2f 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 2d9ead93a2..a9d19a5574 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index b012443370..8adc23f826 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -9,3 +9,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y
This patch enables SiFive UART driver in all QEMU RISC-V defconfigs. Signed-off-by: Anup Patel <anup@brainfault.org> --- configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv64_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + 4 files changed, 4 insertions(+)