diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index ae5e225..79af701 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -769,4 +769,94 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base,
 #define L3_PRD_PURGE_TTYPE_MASK 		PPC_BIT(1) | PPC_BIT(2) | PPC_BIT(3) | PPC_BIT(4)
 #define L3_FULL_PURGE				0x0
 
+/* Debug registers for NPU2 HMI */
+#define NPU_STCK0_CS_SM0_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x1017)
+#define NPU_STCK0_CS_SM1_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x1047)
+#define NPU_STCK0_CS_SM2_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x1077)
+#define NPU_STCK0_CS_SM3_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x10A7)
+#define NPU_STCK1_CS_SM0_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x1217)
+#define NPU_STCK1_CS_SM1_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x1247)
+#define NPU_STCK1_CS_SM2_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x1277)
+#define NPU_STCK1_CS_SM3_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x12A7)
+#define NPU_STCK2_CS_SM0_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x1417)
+#define NPU_STCK2_CS_SM1_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x1447)
+#define NPU_STCK2_CS_SM2_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x1477)
+#define NPU_STCK2_CS_SM3_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x14A7)
+#define NPU_STCK0_CS_CTL_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x10DA)
+#define NPU_STCK1_CS_CTL_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x12DA)
+#define NPU_STCK2_CS_CTL_MISC_CERR_FIRST0	NPU2_REG_OFFSET(0x50, 1, 0x14DA)
+#define NPU_STCK0_CS_CTL_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x10DB)
+#define NPU_STCK1_CS_CTL_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x12DB)
+#define NPU_STCK2_CS_CTL_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x14DB)
+#define NPU_STCK0_CS_SM0_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x1011)
+#define NPU_STCK0_CS_SM1_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x1041)
+#define NPU_STCK0_CS_SM2_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x1071)
+#define NPU_STCK0_CS_SM3_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x10A1)
+#define NPU_STCK1_CS_SM0_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x1211)
+#define NPU_STCK1_CS_SM1_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x1241)
+#define NPU_STCK1_CS_SM2_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x1271)
+#define NPU_STCK1_CS_SM3_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x12A1)
+#define NPU_STCK2_CS_SM0_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x1411)
+#define NPU_STCK2_CS_SM1_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x1441)
+#define NPU_STCK2_CS_SM2_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x1471)
+#define NPU_STCK2_CS_SM3_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x14A1)
+#define NPU_STCK0_CS_SM0_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x1018)
+#define NPU_STCK0_CS_SM1_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x1048)
+#define NPU_STCK0_CS_SM2_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x1078)
+#define NPU_STCK0_CS_SM3_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x10A8)
+#define NPU_STCK1_CS_SM0_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x1218)
+#define NPU_STCK1_CS_SM1_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x1248)
+#define NPU_STCK1_CS_SM2_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x1278)
+#define NPU_STCK1_CS_SM3_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x12A8)
+#define NPU_STCK2_CS_SM0_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x1418)
+#define NPU_STCK2_CS_SM1_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x1448)
+#define NPU_STCK2_CS_SM2_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x1478)
+#define NPU_STCK2_CS_SM3_MISC_CERR_FIRST1	NPU2_REG_OFFSET(0x50, 1, 0x14A8)
+#define NPU_XTS_REG_ERR_HOLD			NPU2_REG_OFFSET(0x50, 1, 0x1640)
+#define NPU_STCK0_NTL0_REGS_CERR_FIRST1		NPU2_REG_OFFSET(0x50, 1, 0x1114)
+#define NPU_STCK0_NTL1_REGS_CERR_FIRST1		NPU2_REG_OFFSET(0x50, 1, 0x1134)
+#define NPU_STCK1_NTL0_REGS_CERR_FIRST1		NPU2_REG_OFFSET(0x50, 1, 0x1314)
+#define NPU_STCK1_NTL1_REGS_CERR_FIRST1		NPU2_REG_OFFSET(0x50, 1, 0x1334)
+#define NPU_STCK2_NTL0_REGS_CERR_FIRST1		NPU2_REG_OFFSET(0x50, 1, 0x1514)
+#define NPU_STCK2_NTL1_REGS_CERR_FIRST1		NPU2_REG_OFFSET(0x50, 1, 0x1534)
+#define NPU_STCK0_NTL0_REGS_CERR_FIRST2		NPU2_REG_OFFSET(0x50, 1, 0x1118)
+#define NPU_STCK0_NTL1_REGS_CERR_FIRST2		NPU2_REG_OFFSET(0x50, 1, 0x1138)
+#define NPU_STCK1_NTL0_REGS_CERR_FIRST2		NPU2_REG_OFFSET(0x50, 1, 0x1318)
+#define NPU_STCK1_NTL1_REGS_CERR_FIRST2		NPU2_REG_OFFSET(0x50, 1, 0x1338)
+#define NPU_STCK2_NTL0_REGS_CERR_FIRST2		NPU2_REG_OFFSET(0x50, 1, 0x1518)
+#define NPU_STCK2_NTL1_REGS_CERR_FIRST2		NPU2_REG_OFFSET(0x50, 1, 0x1538)
+#define NPU_STCK0_CS_CTL_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x10D8)
+#define NPU_STCK1_CS_CTL_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x12D8)
+#define NPU_STCK2_CS_CTL_MISC_CERR_MESSAGE0	NPU2_REG_OFFSET(0x50, 1, 0x14D8)
+#define NPU_STCK0_CS_CTL_MISC_CERR_MESSAGE1	NPU2_REG_OFFSET(0x50, 1, 0x10D9)
+#define NPU_STCK1_CS_CTL_MISC_CERR_MESSAGE1	NPU2_REG_OFFSET(0x50, 1, 0x12D9)
+#define NPU_STCK2_CS_CTL_MISC_CERR_MESSAGE1	NPU2_REG_OFFSET(0x50, 1, 0x14D9)
+#define NPU_STCK0_CS_SM0_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x1019)
+#define NPU_STCK0_CS_SM1_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x1049)
+#define NPU_STCK0_CS_SM2_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x1079)
+#define NPU_STCK0_CS_SM3_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x10A9)
+#define NPU_STCK1_CS_SM0_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x1219)
+#define NPU_STCK1_CS_SM1_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x1249)
+#define NPU_STCK1_CS_SM2_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x1279)
+#define NPU_STCK1_CS_SM3_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x12A9)
+#define NPU_STCK2_CS_SM0_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x1419)
+#define NPU_STCK2_CS_SM1_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x1449)
+#define NPU_STCK2_CS_SM2_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x1479)
+#define NPU_STCK2_CS_SM3_MISC_CERR_FIRST2	NPU2_REG_OFFSET(0x50, 1, 0x14A9)
+#define NPU_STCK0_DAT_MISC_CERR_ECC_HOLD	NPU2_REG_OFFSET(0x50, 1, 0x10F4)
+#define NPU_STCK1_DAT_MISC_CERR_ECC_HOLD	NPU2_REG_OFFSET(0x50, 1, 0x12F4)
+#define NPU_STCK2_DAT_MISC_CERR_ECC_HOLD	NPU2_REG_OFFSET(0x50, 1, 0x14F4)
+#define NPU_STCK0_DAT_MISC_CERR_ECC_MASK	NPU2_REG_OFFSET(0x50, 1, 0x10F5)
+#define NPU_STCK1_DAT_MISC_CERR_ECC_MASK	NPU2_REG_OFFSET(0x50, 1, 0x12F5)
+#define NPU_STCK2_DAT_MISC_CERR_ECC_MASK	NPU2_REG_OFFSET(0x50, 1, 0x14F5)
+#define NPU_STCK0_DAT_MISC_CERR_ECC_FIRST	NPU2_REG_OFFSET(0x50, 1, 0x10F6)
+#define NPU_STCK1_DAT_MISC_CERR_ECC_FIRST	NPU2_REG_OFFSET(0x50, 1, 0x12F6)
+#define NPU_STCK2_DAT_MISC_CERR_ECC_FIRST	NPU2_REG_OFFSET(0x50, 1, 0x14F6)
+#define NPU_STCK0_DAT_MISC_REM0			NPU2_REG_OFFSET(0x50, 1, 0x10FD)
+#define NPU_STCK1_DAT_MISC_REM0			NPU2_REG_OFFSET(0x50, 1, 0x12FD)
+#define NPU_STCK2_DAT_MISC_REM0			NPU2_REG_OFFSET(0x50, 1, 0x14FD)
+#define NPU_STCK0_DAT_MISC_REM1			NPU2_REG_OFFSET(0x50, 1, 0x10FE)
+#define NPU_STCK1_DAT_MISC_REM1			NPU2_REG_OFFSET(0x50, 1, 0x12FE)
+#define NPU_STCK2_DAT_MISC_REM1			NPU2_REG_OFFSET(0x50, 1, 0x14FE)
+
 #endif /* __NPU2_REGS_H */
diff --git a/core/hmi.c b/core/hmi.c
index c01a2c3..ef50e4c 100644
--- a/core/hmi.c
+++ b/core/hmi.c
@@ -594,56 +594,118 @@ static void find_nx_checkstop_reason(int flat_chip_id,
 	queue_hmi_event(hmi_evt, 0, out_flags);
 }
 
-/*
- * If the year is 2018 and you still see all these hardcoded, you
- * should really replace this with the neat macros that's in the
- * NPU2 code rather than this horrible listing of every single
- * NPU2 register hardcoded for a specific chip.
- *
- * I feel dirty having even written it.
- */
-static uint32_t npu2_scom_dump[] = {
-	0x5011017, 0x5011047, 0x5011077, 0x50110A7,
-	0x5011217, 0x5011247, 0x5011277, 0x50112A7,
-	0x5011417, 0x5011447, 0x5011477, 0x50114A7,
-	0x50110DA, 0x50112DA, 0x50114DA,
-	0x50110DB, 0x50112DB, 0x50114DB,
-	0x5011011, 0x5011041, 0x5011071, 0x50110A1,
-	0x5011211, 0x5011241, 0x5011271, 0x50112A1,
-	0x5011411, 0x5011441, 0x5011471, 0x50114A1,
-	0x5011018, 0x5011048, 0x5011078, 0x50110A8,
-	0x5011218, 0x5011248, 0x5011278, 0x50112A8,
-	0x5011418, 0x5011448, 0x5011478, 0x50114A8,
-	0x5011640,
-	0x5011114, 0x5011134, 0x5011314, 0x5011334,
-	0x5011514, 0x5011534, 0x5011118, 0x5011138,
-	0x5011318, 0x5011338, 0x5011518, 0x5011538,
-	0x50110D8, 0x50112D8, 0x50114D8,
-	0x50110D9, 0x50112D9, 0x50114D9,
-	0x5011019, 0x5011049, 0x5011079, 0x50110A9,
-	0x5011219, 0x5011249, 0x5011279, 0x50112A9,
-	0x5011419, 0x5011449, 0x5011479, 0x50114A9,
-	0x50110F4, 0x50112F4, 0x50114F4,
-	0x50110F5, 0x50112F5, 0x50114F5,
-	0x50110F6, 0x50112F6, 0x50114F6,
-	0x50110FD, 0x50112FD, 0x50114FD,
-	0x50110FE, 0x50112FE, 0x50114FE,
-	0x00
+typedef struct {
+	uint32_t reg;
+	const char *name;
+} npu2_scom_dump_t;
+
+static npu2_scom_dump_t npu2_scom_dump[] = {
+#define __NPU2_SCOM_DUMP(x)	{ x, #x }
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM0_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM1_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM2_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM3_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM0_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM1_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM2_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM3_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM0_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM1_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM2_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM3_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_CTL_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_CTL_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_CTL_MISC_CERR_FIRST0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_CTL_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_CTL_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_CTL_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM0_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM1_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM2_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM3_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM0_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM1_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM2_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM3_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM0_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM1_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM2_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM3_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM0_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM1_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM2_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM3_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM0_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM1_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM2_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM3_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM0_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM1_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM2_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM3_MISC_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_XTS_REG_ERR_HOLD),
+	__NPU2_SCOM_DUMP(NPU_STCK0_NTL0_REGS_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK0_NTL1_REGS_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK1_NTL0_REGS_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK1_NTL1_REGS_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK2_NTL0_REGS_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK2_NTL1_REGS_CERR_FIRST1),
+	__NPU2_SCOM_DUMP(NPU_STCK0_NTL0_REGS_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK0_NTL1_REGS_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK1_NTL0_REGS_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK1_NTL1_REGS_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK2_NTL0_REGS_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK2_NTL1_REGS_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_CTL_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_CTL_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_CTL_MISC_CERR_MESSAGE0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_CTL_MISC_CERR_MESSAGE1),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_CTL_MISC_CERR_MESSAGE1),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_CTL_MISC_CERR_MESSAGE1),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM0_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM1_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM2_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK0_CS_SM3_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM0_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM1_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM2_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK1_CS_SM3_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM0_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM1_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM2_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK2_CS_SM3_MISC_CERR_FIRST2),
+	__NPU2_SCOM_DUMP(NPU_STCK0_DAT_MISC_CERR_ECC_HOLD),
+	__NPU2_SCOM_DUMP(NPU_STCK1_DAT_MISC_CERR_ECC_HOLD),
+	__NPU2_SCOM_DUMP(NPU_STCK2_DAT_MISC_CERR_ECC_HOLD),
+	__NPU2_SCOM_DUMP(NPU_STCK0_DAT_MISC_CERR_ECC_MASK),
+	__NPU2_SCOM_DUMP(NPU_STCK1_DAT_MISC_CERR_ECC_MASK),
+	__NPU2_SCOM_DUMP(NPU_STCK2_DAT_MISC_CERR_ECC_MASK),
+	__NPU2_SCOM_DUMP(NPU_STCK0_DAT_MISC_CERR_ECC_FIRST),
+	__NPU2_SCOM_DUMP(NPU_STCK1_DAT_MISC_CERR_ECC_FIRST),
+	__NPU2_SCOM_DUMP(NPU_STCK2_DAT_MISC_CERR_ECC_FIRST),
+	__NPU2_SCOM_DUMP(NPU_STCK0_DAT_MISC_REM0),
+	__NPU2_SCOM_DUMP(NPU_STCK1_DAT_MISC_REM0),
+	__NPU2_SCOM_DUMP(NPU_STCK2_DAT_MISC_REM0),
+	__NPU2_SCOM_DUMP(NPU_STCK0_DAT_MISC_REM1),
+	__NPU2_SCOM_DUMP(NPU_STCK1_DAT_MISC_REM1),
+	__NPU2_SCOM_DUMP(NPU_STCK2_DAT_MISC_REM1),
+	{ 0x00, NULL }
 };
 
-static void dump_scoms(int flat_chip_id, const char *unit, uint32_t *scoms,
-			const char *loc)
+static void dump_scoms(int flat_chip_id, const char *unit,
+		       npu2_scom_dump_t *scoms, const char *loc)
 {
 	uint64_t value;
 	int r;
 
-	while (*scoms != 0) {
+	while (scoms->reg) {
 		value = 0;
-		r = _xscom_read(flat_chip_id, *scoms, &value, false);
+		r = _xscom_read(flat_chip_id, scoms->reg, &value, false);
 		if (r != OPAL_SUCCESS)
 			continue;
-		prlog(PR_ERR, "%s: [Loc: %s] P:%d 0x%08x=0x%016llx\n",
-		      unit, loc, flat_chip_id, *scoms, value);
+		if (value)
+			prlog(PR_ERR, "%s: [Loc: %s] P:%d %s=0x%016llx\n",
+			      unit, loc, flat_chip_id, scoms->name, value);
 		scoms++;
 	}
 }
