From patchwork Fri Jun 17 09:30:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aneesh V X-Patchwork-Id: 100780 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A8DCFB6F9E for ; Fri, 17 Jun 2011 19:39:37 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C18CB280E6; Fri, 17 Jun 2011 11:39:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4PaTLHRF9sc9; Fri, 17 Jun 2011 11:39:14 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0564C280D3; Fri, 17 Jun 2011 11:38:40 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 23C38280B4 for ; Fri, 17 Jun 2011 11:38:36 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SeLXqpZvjFdL for ; Fri, 17 Jun 2011 11:38:33 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 9C2BD280A5 for ; Fri, 17 Jun 2011 11:38:32 +0200 (CEST) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p5H9cL8J027631 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 17 Jun 2011 04:38:23 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p5H9cK7l021584; Fri, 17 Jun 2011 15:08:20 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Fri, 17 Jun 2011 15:08:20 +0530 Received: from localhost (a0393566pc.apr.dhcp.ti.com [172.24.137.55]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p5H9cH5c015367; Fri, 17 Jun 2011 15:08:18 +0530 (IST) From: Aneesh V To: Date: Fri, 17 Jun 2011 15:00:50 +0530 Message-ID: <1308303054-8727-6-git-send-email-aneesh@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1299589658-30896-1-git-send-email-aneesh@ti.com> References: <1299589658-30896-1-git-send-email-aneesh@ti.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 5/9] arm: minor fixes for cache and mmu handling X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de 1. make sure that page table setup is not done multiple times 2. flush_dcache_all() is more appropriate while disabling cache than a range flush on the entire memory(flush_cache()) Provide a default implementation for flush_dcache_all() for backward compatibility and to avoid build issues. Signed-off-by: Aneesh V --- V2: * Fixed signature of flush_cache in cache.c --- arch/arm/lib/cache-cp15.c | 9 +++++++-- arch/arm/lib/cache.c | 11 +++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 51831a9..e6c3eae 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -92,13 +92,18 @@ static inline void mmu_setup(void) set_cr(reg | CR_M); } +static int mmu_enabled(void) +{ + return get_cr() & CR_M; +} + /* cache_bit must be either CR_I or CR_C */ static void cache_enable(uint32_t cache_bit) { uint32_t reg; /* The data cache is not active unless the mmu is enabled too */ - if (cache_bit == CR_C) + if ((cache_bit == CR_C) && !mmu_enabled()) mmu_setup(); reg = get_cr(); /* get control reg. */ cp_delay(); @@ -117,7 +122,7 @@ static void cache_disable(uint32_t cache_bit) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; - flush_cache(0, ~0); + flush_dcache_all(); } reg = get_cr(); cp_delay(); diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index dc3242c..92b61a2 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -42,3 +42,14 @@ void __flush_cache(unsigned long start, unsigned long size) } void flush_cache(unsigned long start, unsigned long size) __attribute__((weak, alias("__flush_cache"))); + +/* + * Default implementation: + * do a range flush for the entire range + */ +void __flush_dcache_all(void) +{ + flush_cache(0, ~0); +} +void flush_dcache_all(void) + __attribute__((weak, alias("__flush_dcache_all")));