| Message ID | 20181204151702.8514-1-jonathan@marek.ca |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [v4,1/5] drm/msm/mdp4: add lcdc-align-lsb flag to control lane alignment | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | "total: 0 errors, 1 warnings, 41 lines checked" |
On Tue, 4 Dec 2018 10:16:57 -0500, Jonathan Marek wrote: > This allows controlling which of the 8 lanes are used for 6 bit color. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > --- > v3: removed empty line and added documentation > > .../devicetree/bindings/display/msm/mdp4.txt | 2 ++ > .../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 21 ++++++++++++------- > 2 files changed, 15 insertions(+), 8 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
On Tue, Dec 4, 2018 at 1:20 PM Jonathan Marek <jonathan@marek.ca> wrote: > > This adds the gpu nodes for the adreno 200 GPU on iMX51 and iMX53, now > supported by the freedreno driver. > > The compatible for the iMX51 uses a patchid of 1, which is used by drm/msm > driver to identify the smaller 128KiB GMEM size. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Fabio Estevam <festevam@gmail.com>
On Tue, Dec 04, 2018 at 10:17:00AM -0500, Jonathan Marek wrote: > This adds the gpu nodes for the adreno 200 GPU on iMX51 and iMX53, now > supported by the freedreno driver. > > The compatible for the iMX51 uses a patchid of 1, which is used by drm/msm > driver to identify the smaller 128KiB GMEM size. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> Applied, thanks.
diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.txt b/Documentation/devicetree/bindings/display/msm/mdp4.txt index 3c341a15c..b07eeb38f 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp4.txt +++ b/Documentation/devicetree/bindings/display/msm/mdp4.txt @@ -38,6 +38,8 @@ Required properties: Optional properties: - clock-names: the following clocks are optional: * "lut_clk" +- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be + used for LCDC. This is only valid for 18bpp panels. Example: diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c index 9e08c2efa..c9e34501a 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c @@ -377,20 +377,25 @@ static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder) unsigned long pc = mdp4_lcdc_encoder->pixclock; struct mdp4_kms *mdp4_kms = get_kms(encoder); struct drm_panel *panel; + uint32_t config; int i, ret; if (WARN_ON(mdp4_lcdc_encoder->enabled)) return; /* TODO: hard-coded for 18bpp: */ - mdp4_crtc_set_config(encoder->crtc, - MDP4_DMA_CONFIG_R_BPC(BPC6) | - MDP4_DMA_CONFIG_G_BPC(BPC6) | - MDP4_DMA_CONFIG_B_BPC(BPC6) | - MDP4_DMA_CONFIG_PACK_ALIGN_MSB | - MDP4_DMA_CONFIG_PACK(0x21) | - MDP4_DMA_CONFIG_DEFLKR_EN | - MDP4_DMA_CONFIG_DITHER_EN); + config = + MDP4_DMA_CONFIG_R_BPC(BPC6) | + MDP4_DMA_CONFIG_G_BPC(BPC6) | + MDP4_DMA_CONFIG_B_BPC(BPC6) | + MDP4_DMA_CONFIG_PACK(0x21) | + MDP4_DMA_CONFIG_DEFLKR_EN | + MDP4_DMA_CONFIG_DITHER_EN; + + if (!of_property_read_bool(dev->dev->of_node, "qcom,lcdc-align-lsb")) + config |= MDP4_DMA_CONFIG_PACK_ALIGN_MSB; + + mdp4_crtc_set_config(encoder->crtc, config); mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0); bs_set(mdp4_lcdc_encoder, 1);
This allows controlling which of the 8 lanes are used for 6 bit color. Signed-off-by: Jonathan Marek <jonathan@marek.ca> --- v3: removed empty line and added documentation .../devicetree/bindings/display/msm/mdp4.txt | 2 ++ .../gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 21 ++++++++++++------- 2 files changed, 15 insertions(+), 8 deletions(-)