[v1,1/2] dt-binding: mtd: add NPCM FIU controller

Message ID 20181203091456.454030-2-tmaimon77@gmail.com
State Not Applicable, archived
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Series
  • SPI-NOR add NPCM FIU controller driver
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Commit Message

Tomer Maimon Dec. 3, 2018, 9:14 a.m.
Added device tree binding documentation for Nuvoton BMC
NPCM Flash Interface Unit(FIU) SPI-NOR controller.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
---
 Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt

Comments

Rob Herring Dec. 19, 2018, 3:54 p.m. | #1
On Mon, Dec 03, 2018 at 11:14:55AM +0200, Tomer Maimon wrote:
> Added device tree binding documentation for Nuvoton BMC
> NPCM Flash Interface Unit(FIU) SPI-NOR controller.
> 
> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> ---
>  Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt
> 
> diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
> new file mode 100644
> index 000000000000..9746cb5b1ced
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
> @@ -0,0 +1,64 @@
> +* Nuvoton FLASH Interface Unit (FIU) SPI Controller
> +
> +NPCM FIU supports single, dual and quad communication interface.
> +
> +The NPCM7XX supports three FIU modules,
> +FIU0 and FIUx supports two chip selects,
> +FIU3 support four chip select.
> +
> +Required properties:
> +  - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
> +  - #address-cells : should be 1.
> +  - #size-cells : should be 0.
> +  - reg : the first contains the register location and length,
> +          the second contains the memory mapping address and length
> +  - reg-names: Should contain the reg names "control" and "memory"
> +  - clocks : phandle of F reference clock.
> +
> +Required properties in case the pins can be muxed:
> +  - pinctrl-names : a pinctrl state named "default" must be defined.
> +  - pinctrl-0 : phandle referencing pin configuration of the device.
> +
> +Optional property:
> +  - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.

Needs a vendor prefix. Unless this is some standard SPI thing (which 
I've never heard of).

> +
> +The SPI device must be a child of the FIU node and must have a
> +compatible property as specified in bindings/mtd/jedec,spi-nor.txt
> +
> +Required property:
> +- reg: chip select number.
> +
> +Optional property:
> +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.
> +
> +Aliases:
> +- All the FIU controller nodes should be represented in the aliases node using
> +  the following format 'fiu{n}' where n is a unique number for the alias.
> +  In the NPCM7XX BMC:
> +  		fiu0 represent fiu 0 controller
> +  		fiu1 represent fiu 3 controller
> +  		fiu2 represent fiu x controller

Please don't make up your own aliases. Use 'spiX' if anything, but 
really, why do you need aliases in the first place?

> +
> +Example:
> +fiu3: fiu@c00000000 {

spi@...

> +	compatible = "nuvoton,npcm750-fiu";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
> +	reg-names = "control", "memory";
> +	clocks = <&clk NPCM7XX_CLK_AHB>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi3_pins>;
> +	spi-nor@0 {
> +		compatible = "jedec,spi-nor";
> +		spi-rx-bus-width = <2>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0>;
> +		partition@0 {
> +			label = "flash_data";
> +			reg = <0x0 0x800000>;
> +		};
> +	};
> +};
> +
> -- 
> 2.14.1
>
Tomer Maimon Dec. 21, 2018, 8:19 a.m. | #2
Hi Rob,

Thanks for your comments,

The spi-nor drivers are moving to spi (spi-mem), I will make sure to modify
the new SPI dt-binding document according your comments once I finish the
work on the new SPI driver.

https://lkml.org/lkml/2018/12/3/545

Happy new year!

Tomer

On Wed, 19 Dec 2018 at 17:54, Rob Herring <robh@kernel.org> wrote:

> On Mon, Dec 03, 2018 at 11:14:55AM +0200, Tomer Maimon wrote:
> > Added device tree binding documentation for Nuvoton BMC
> > NPCM Flash Interface Unit(FIU) SPI-NOR controller.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> >  Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64
> ++++++++++++++++++++++
> >  1 file changed, 64 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
> b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
> > new file mode 100644
> > index 000000000000..9746cb5b1ced
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
> > @@ -0,0 +1,64 @@
> > +* Nuvoton FLASH Interface Unit (FIU) SPI Controller
> > +
> > +NPCM FIU supports single, dual and quad communication interface.
> > +
> > +The NPCM7XX supports three FIU modules,
> > +FIU0 and FIUx supports two chip selects,
> > +FIU3 support four chip select.
> > +
> > +Required properties:
> > +  - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
> > +  - #address-cells : should be 1.
> > +  - #size-cells : should be 0.
> > +  - reg : the first contains the register location and length,
> > +          the second contains the memory mapping address and length
> > +  - reg-names: Should contain the reg names "control" and "memory"
> > +  - clocks : phandle of F reference clock.
> > +
> > +Required properties in case the pins can be muxed:
> > +  - pinctrl-names : a pinctrl state named "default" must be defined.
> > +  - pinctrl-0 : phandle referencing pin configuration of the device.
> > +
> > +Optional property:
> > +  - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
>
> Needs a vendor prefix. Unless this is some standard SPI thing (which
> I've never heard of).
>
> > +
> > +The SPI device must be a child of the FIU node and must have a
> > +compatible property as specified in bindings/mtd/jedec,spi-nor.txt
> > +
> > +Required property:
> > +- reg: chip select number.
> > +
> > +Optional property:
> > +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.
> > +
> > +Aliases:
> > +- All the FIU controller nodes should be represented in the aliases
> node using
> > +  the following format 'fiu{n}' where n is a unique number for the
> alias.
> > +  In the NPCM7XX BMC:
> > +             fiu0 represent fiu 0 controller
> > +             fiu1 represent fiu 3 controller
> > +             fiu2 represent fiu x controller
>
> Please don't make up your own aliases. Use 'spiX' if anything, but
> really, why do you need aliases in the first place?
>
> > +
> > +Example:
> > +fiu3: fiu@c00000000 {
>
> spi@...
>
> > +     compatible = "nuvoton,npcm750-fiu";
> > +     #address-cells = <1>;
> > +     #size-cells = <0>;
> > +     reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
> > +     reg-names = "control", "memory";
> > +     clocks = <&clk NPCM7XX_CLK_AHB>;
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&spi3_pins>;
> > +     spi-nor@0 {
> > +             compatible = "jedec,spi-nor";
> > +             spi-rx-bus-width = <2>;
> > +             #address-cells = <1>;
> > +             #size-cells = <1>;
> > +             reg = <0>;
> > +             partition@0 {
> > +                     label = "flash_data";
> > +                     reg = <0x0 0x800000>;
> > +             };
> > +     };
> > +};
> > +
> > --
> > 2.14.1
> >
>
<div dir="ltr"><div dir="ltr">Hi Rob,<div><br></div><div>Thanks for your comments,</div><div><br></div><div>The spi-nor drivers are moving to spi (spi-mem), I will make sure to modify the new SPI dt-binding document according your comments once I finish the work on the new SPI driver.</div><div><br></div><div><a href="https://lkml.org/lkml/2018/12/3/545">https://lkml.org/lkml/2018/12/3/545</a><br></div><div><br></div><div>Happy new year!</div><div><br></div><div>Tomer</div></div></div><br><div class="gmail_quote"><div dir="ltr">On Wed, 19 Dec 2018 at 17:54, Rob Herring &lt;<a href="mailto:robh@kernel.org">robh@kernel.org</a>&gt; wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">On Mon, Dec 03, 2018 at 11:14:55AM +0200, Tomer Maimon wrote:<br>
&gt; Added device tree binding documentation for Nuvoton BMC<br>
&gt; NPCM Flash Interface Unit(FIU) SPI-NOR controller.<br>
&gt; <br>
&gt; Signed-off-by: Tomer Maimon &lt;<a href="mailto:tmaimon77@gmail.com" target="_blank">tmaimon77@gmail.com</a>&gt;<br>
&gt; ---<br>
&gt;  Documentation/devicetree/bindings/mtd/npcm-fiu.txt | 64 ++++++++++++++++++++++<br>
&gt;  1 file changed, 64 insertions(+)<br>
&gt;  create mode 100644 Documentation/devicetree/bindings/mtd/npcm-fiu.txt<br>
&gt; <br>
&gt; diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt<br>
&gt; new file mode 100644<br>
&gt; index 000000000000..9746cb5b1ced<br>
&gt; --- /dev/null<br>
&gt; +++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt<br>
&gt; @@ -0,0 +1,64 @@<br>
&gt; +* Nuvoton FLASH Interface Unit (FIU) SPI Controller<br>
&gt; +<br>
&gt; +NPCM FIU supports single, dual and quad communication interface.<br>
&gt; +<br>
&gt; +The NPCM7XX supports three FIU modules,<br>
&gt; +FIU0 and FIUx supports two chip selects,<br>
&gt; +FIU3 support four chip select.<br>
&gt; +<br>
&gt; +Required properties:<br>
&gt; +  - compatible : &quot;nuvoton,npcm750-fiu&quot; for the NPCM7XX BMC<br>
&gt; +  - #address-cells : should be 1.<br>
&gt; +  - #size-cells : should be 0.<br>
&gt; +  - reg : the first contains the register location and length,<br>
&gt; +          the second contains the memory mapping address and length<br>
&gt; +  - reg-names: Should contain the reg names &quot;control&quot; and &quot;memory&quot;<br>
&gt; +  - clocks : phandle of F reference clock.<br>
&gt; +<br>
&gt; +Required properties in case the pins can be muxed:<br>
&gt; +  - pinctrl-names : a pinctrl state named &quot;default&quot; must be defined.<br>
&gt; +  - pinctrl-0 : phandle referencing pin configuration of the device.<br>
&gt; +<br>
&gt; +Optional property:<br>
&gt; +  - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.<br>
<br>
Needs a vendor prefix. Unless this is some standard SPI thing (which <br>
I&#39;ve never heard of).<br>
<br>
&gt; +<br>
&gt; +The SPI device must be a child of the FIU node and must have a<br>
&gt; +compatible property as specified in bindings/mtd/jedec,spi-nor.txt<br>
&gt; +<br>
&gt; +Required property:<br>
&gt; +- reg: chip select number.<br>
&gt; +<br>
&gt; +Optional property:<br>
&gt; +- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.<br>
&gt; +<br>
&gt; +Aliases:<br>
&gt; +- All the FIU controller nodes should be represented in the aliases node using<br>
&gt; +  the following format &#39;fiu{n}&#39; where n is a unique number for the alias.<br>
&gt; +  In the NPCM7XX BMC:<br>
&gt; +             fiu0 represent fiu 0 controller<br>
&gt; +             fiu1 represent fiu 3 controller<br>
&gt; +             fiu2 represent fiu x controller<br>
<br>
Please don&#39;t make up your own aliases. Use &#39;spiX&#39; if anything, but <br>
really, why do you need aliases in the first place?<br>
<br>
&gt; +<br>
&gt; +Example:<br>
&gt; +fiu3: fiu@c00000000 {<br>
<br>
spi@...<br>
<br>
&gt; +     compatible = &quot;nuvoton,npcm750-fiu&quot;;<br>
&gt; +     #address-cells = &lt;1&gt;;<br>
&gt; +     #size-cells = &lt;0&gt;;<br>
&gt; +     reg = &lt;0xfb000000 0x1000&gt;, &lt;0x80000000 0x10000000&gt;;<br>
&gt; +     reg-names = &quot;control&quot;, &quot;memory&quot;;<br>
&gt; +     clocks = &lt;&amp;clk NPCM7XX_CLK_AHB&gt;;<br>
&gt; +     pinctrl-names = &quot;default&quot;;<br>
&gt; +     pinctrl-0 = &lt;&amp;spi3_pins&gt;;<br>
&gt; +     spi-nor@0 {<br>
&gt; +             compatible = &quot;jedec,spi-nor&quot;;<br>
&gt; +             spi-rx-bus-width = &lt;2&gt;;<br>
&gt; +             #address-cells = &lt;1&gt;;<br>
&gt; +             #size-cells = &lt;1&gt;;<br>
&gt; +             reg = &lt;0&gt;;<br>
&gt; +             partition@0 {<br>
&gt; +                     label = &quot;flash_data&quot;;<br>
&gt; +                     reg = &lt;0x0 0x800000&gt;;<br>
&gt; +             };<br>
&gt; +     };<br>
&gt; +};<br>
&gt; +<br>
&gt; -- <br>
&gt; 2.14.1<br>
&gt; <br>
</blockquote></div>

Patch

diff --git a/Documentation/devicetree/bindings/mtd/npcm-fiu.txt b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
new file mode 100644
index 000000000000..9746cb5b1ced
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/npcm-fiu.txt
@@ -0,0 +1,64 @@ 
+* Nuvoton FLASH Interface Unit (FIU) SPI Controller
+
+NPCM FIU supports single, dual and quad communication interface.
+
+The NPCM7XX supports three FIU modules,
+FIU0 and FIUx supports two chip selects,
+FIU3 support four chip select.
+
+Required properties:
+  - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC
+  - #address-cells : should be 1.
+  - #size-cells : should be 0.
+  - reg : the first contains the register location and length,
+          the second contains the memory mapping address and length
+  - reg-names: Should contain the reg names "control" and "memory"
+  - clocks : phandle of F reference clock.
+
+Required properties in case the pins can be muxed:
+  - pinctrl-names : a pinctrl state named "default" must be defined.
+  - pinctrl-0 : phandle referencing pin configuration of the device.
+
+Optional property:
+  - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
+
+The SPI device must be a child of the FIU node and must have a
+compatible property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Required property:
+- reg: chip select number.
+
+Optional property:
+- spi-rx-bus-width: see ../spi/spi-bus.txt for the description.
+
+Aliases:
+- All the FIU controller nodes should be represented in the aliases node using
+  the following format 'fiu{n}' where n is a unique number for the alias.
+  In the NPCM7XX BMC:
+  		fiu0 represent fiu 0 controller
+  		fiu1 represent fiu 3 controller
+  		fiu2 represent fiu x controller
+
+Example:
+fiu3: fiu@c00000000 {
+	compatible = "nuvoton,npcm750-fiu";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
+	reg-names = "control", "memory";
+	clocks = <&clk NPCM7XX_CLK_AHB>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi3_pins>;
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		partition@0 {
+			label = "flash_data";
+			reg = <0x0 0x800000>;
+		};
+	};
+};
+