From patchwork Sun Dec 2 19:35:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1006537 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="P1Jdt+a6"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437JJz0rGpz9s47 for ; Mon, 3 Dec 2018 06:36:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725789AbeLBTgV (ORCPT ); Sun, 2 Dec 2018 14:36:21 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:56093 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725710AbeLBTgV (ORCPT ); Sun, 2 Dec 2018 14:36:21 -0500 Received: by mail-wm1-f66.google.com with SMTP id y139so3624594wmc.5; Sun, 02 Dec 2018 11:36:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KNjplkWp4FhWYBXQ2412QnbOBs5cnYg14L4PmMlOMVg=; b=P1Jdt+a6EIqaOBwR9sJDafFLkMP1W4kWaUB7MxQ/tKXuO2e4ORr+HeEcEnErCsovJR XdzfVOBnjHGYSHuqO1uaaU87NVL4AyRKY8nR+/kOeLHkGO3662AMJnyg8Kzt3VdQmnUS /+x57ZBACynJyEnyymTz7VA75xpSZwtc3fdUcYJzFOPFFpgGtlDvyDXWSIwjdL52uHIj zMPxaM6SfOZ1jqOU5by1hCrPx03rbmI4g6pz01njbEiA6j0Ie9xx8mswpziwg8RD4tOB JhHIZnNX+IaC2PAc4tF6fRw3FToCRmKeQhgINEtR34Z733mUgTGl/a0LGgNo1B2QDTUa QMNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KNjplkWp4FhWYBXQ2412QnbOBs5cnYg14L4PmMlOMVg=; b=eU04hjqd3jlWgvpyd+O73OHeJabL7ttlD4gS1yyZoLcd07ngmQI2Qktf892R2q7hur wWrlGVgTC67Io9UWYsTdSgfva50yjwkfeNYS6D+TvAPHLg0sEbW719oxRGdZtzhD/luY 69uJgcSTLPPjuMogQWPjLGzwszFBLQu432zLrj/5fufn/edqtjZH87SF+rCROotFnrpb teMlALcfiMhrnnrQ4tSSPC/KSLs3ksifhtGVVx3ZgziDy5bKbcyGd8HPDSwsJ7K2lY4i wsPxw3gdszT8Dtlc2d4ZScUDHcYzsZAf44zAeyz4eo+giN+8cJ1rt4yKyhVHZi++PONQ IA2g== X-Gm-Message-State: AA+aEWaCfl4D/W7/9xwpdX10E9dSDJhYsEboBi79yr/68yiF4YJWC4/2 C+gieUO7ZOuNpmFtPitRy/bWhd0K X-Google-Smtp-Source: AFSGD/UuliWu8MTyv7lYDai2/B2CjNp2m2Opc3nGxRlRMA6zBZtEn1urbs3b5olpB/gy17Xu0kh/Yg== X-Received: by 2002:a1c:9e4a:: with SMTP id h71mr2494583wme.82.1543779375944; Sun, 02 Dec 2018 11:36:15 -0800 (PST) Received: from kurokawa.lan (ip-86-49-110-70.net.upcbroadband.cz. [86.49.110.70]) by smtp.gmail.com with ESMTPSA id y185sm4016628wmg.34.2018.12.02.11.36.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 11:36:14 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, Marek Vasut , Linus Walleij , Bartosz Golaszewski Subject: [PATCH 05/14] gpio: pca953x: Unify pca953x_{read, write}_regs_{16, 24}() Date: Sun, 2 Dec 2018 20:35:44 +0100 Message-Id: <20181202193553.29704-5-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181202193553.29704-1-marek.vasut+renesas@gmail.com> References: <20181202193553.29704-1-marek.vasut+renesas@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org At this point, these two functions only differ in whether they do or do not set the address increment bit. The 16 GPIO case does not need to set the AI bit, except for PCA9575 on write, while the 24 GPIO and more case does set the AI bit always. Merge these two functions together to simplify the code a bit. Signed-off-by: Marek Vasut Cc: Linus Walleij Cc: Bartosz Golaszewski --- drivers/gpio/gpio-pca953x.c | 49 ++++++++++++++----------------------- 1 file changed, 18 insertions(+), 31 deletions(-) diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 2e02b3a9ac48..551fa69661b2 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -206,9 +206,16 @@ static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val) return i2c_smbus_write_byte_data(chip->client, reg, *val); } -static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) +static int pca953x_write_regs_mul(struct pca953x_chip *chip, int reg, u8 *val) { - u32 regaddr = (reg << 1); + int bank_shift = pca953x_bank_shift(chip); + int addr = (reg & PCAL_GPIO_MASK) << bank_shift; + int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; + u8 regaddr = pinctrl | addr; + + /* Chips with 24 and more GPIOs always support Auto Increment */ + if (NBANK(chip) > 2) + regaddr |= REG_ADDR_AI; /* PCA9575 needs address-increment on multi-byte writes */ if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) @@ -218,17 +225,6 @@ static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) NBANK(chip), val); } -static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) -{ - int bank_shift = pca953x_bank_shift(chip); - int addr = (reg & PCAL_GPIO_MASK) << bank_shift; - int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; - - return i2c_smbus_write_i2c_block_data(chip->client, - pinctrl | addr | REG_ADDR_AI, - NBANK(chip), val); -} - static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val) { int ret = 0; @@ -252,24 +248,18 @@ static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val) return ret; } -static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val) -{ - int ret; - - ret = i2c_smbus_read_word_data(chip->client, reg << 1); - put_unaligned(ret, (u16 *)val); - - return ret; -} - -static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val) +static int pca953x_read_regs_mul(struct pca953x_chip *chip, int reg, u8 *val) { int bank_shift = pca953x_bank_shift(chip); int addr = (reg & PCAL_GPIO_MASK) << bank_shift; int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; + u8 regaddr = pinctrl | addr; + + /* Chips with 24 and more GPIOs always support Auto Increment */ + if (NBANK(chip) > 2) + regaddr |= REG_ADDR_AI; - return i2c_smbus_read_i2c_block_data(chip->client, - pinctrl | addr | REG_ADDR_AI, + return i2c_smbus_read_i2c_block_data(chip->client, regaddr, NBANK(chip), val); } @@ -885,12 +875,9 @@ static int pca953x_probe(struct i2c_client *client, if (chip->gpio_chip.ngpio <= 8) { chip->write_regs = pca953x_write_regs_8; chip->read_regs = pca953x_read_regs_8; - } else if (chip->gpio_chip.ngpio >= 24) { - chip->write_regs = pca953x_write_regs_24; - chip->read_regs = pca953x_read_regs_24; } else { - chip->write_regs = pca953x_write_regs_16; - chip->read_regs = pca953x_read_regs_16; + chip->write_regs = pca953x_write_regs_mul; + chip->read_regs = pca953x_read_regs_mul; } if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)