From patchwork Sun Dec 2 19:35:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 1006535 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="krEXoI3h"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437JJx49qSz9s47 for ; Mon, 3 Dec 2018 06:36:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725788AbeLBTgU (ORCPT ); Sun, 2 Dec 2018 14:36:20 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:33511 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725710AbeLBTgT (ORCPT ); Sun, 2 Dec 2018 14:36:19 -0500 Received: by mail-wm1-f67.google.com with SMTP id r24so5445732wmh.0; Sun, 02 Dec 2018 11:36:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Rm7z5Cjr3bXWI9Di4Ky6yJyaTa48zHt711qZrvk7FI8=; b=krEXoI3hFHpr1/qe9Y2v1Wv84Kd0KXe/+CKtayHeXKAvf43SW5/HfMJD/AUI6QUCKC n+IfU++uUPYK5m56h9VKFfnnMtOPqNqVtV4Cc/jN4g1mjIhftOfzWI9a5659BeDOY0rD 5RYsaUeI9HzEYgMghaHs2CVdORZ2EFqPBAWMrNVbpkK9zub4Hn8SV4t3Gqa09HJ8JDVY qFE3o6xXwoSXw+hnorTh+X7Jb9Xd8S7YozDsPjpxPPQLHFvEvSm3z5m2YySsAJKZX73b c8YBvALEAOqb1HlMydSbJwDUFBQajWarlyk9sYZjY/uj+h254AVoPOsZFheWnKIFgrd5 xuTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Rm7z5Cjr3bXWI9Di4Ky6yJyaTa48zHt711qZrvk7FI8=; b=uipV9/NtS+aSaoLsQG2SGj1vnvmkY8sOwR35w6vAMh7kNctAW1ZyIZQRc+ffEMICn3 WNHjW3pWezpI9mCdJVV5WpkrYcgBpfPmgjbLNABhHTApHgKLcOric2qVe6MCOnDLZXoB WcPYjZbE/77g8DO0YOr1ZxzuZ+zvSeIf9NpKje8MJJ8fwfvDDREiBbAUzkL1aKudi/bl dYMMM1a1lHs1eaXwMWkiUNeogBNfbxbP82EakYFXHBGZCXbjnMr+EhyfVWJWygOFNAz0 /LObMvXZhmBoTngu0Z08haISBhNzIa105Wk5Kp5HR3EN11rqgIVuc6sTV+FA7zxzQ+KC LHNQ== X-Gm-Message-State: AA+aEWbNwPx7Dxu5DqI3OAokxVMYbAGau6w1j6wCrTxWN3CUPxrHn3Tp 1HamD3vz8fwzNg4q+y3+UDP1Ij2C X-Google-Smtp-Source: AFSGD/U7SaU6sfErAkV9byrOpLYoL69p2+iiqyl8hmCAWkMGxEPXIi5MwBJFS6L+UqYlb5uRJfNq4A== X-Received: by 2002:a1c:35c5:: with SMTP id c188mr6063346wma.134.1543779373344; Sun, 02 Dec 2018 11:36:13 -0800 (PST) Received: from kurokawa.lan (ip-86-49-110-70.net.upcbroadband.cz. [86.49.110.70]) by smtp.gmail.com with ESMTPSA id y185sm4016628wmg.34.2018.12.02.11.36.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 11:36:12 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: linux-gpio@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, Marek Vasut , Linus Walleij , Bartosz Golaszewski Subject: [PATCH 03/14] gpio: pca953x: Repair multi-byte IO address increment on PCA9575 Date: Sun, 2 Dec 2018 20:35:42 +0100 Message-Id: <20181202193553.29704-3-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181202193553.29704-1-marek.vasut+renesas@gmail.com> References: <20181202193553.29704-1-marek.vasut+renesas@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The multi-byte IO on various pca953x chips requires the auto-increment bit, while other chips toggle the LSbit automatically. Note that LSbit toggling only alternates between two registers during the IO, it is not the same as address auto-increment. The driver currently assumes that #gpios > 16 implies auto-increment, while #gpios <= 16 implies LSbit toggling. This is incorrect at there are chips with 16 GPIOs which require the auto-increment bit. The PCA9575, according to NXP datasheet rev. 4.2 from 16 April 2015, section 7.3 Command Register, the bit 7 in command register is the auto-increment bit, which allows programming multiple registers sequentially. Set this bit both in pca953x_gpio_set_multiple(), where it fixes the multi register programming, and in pca957x_write_regs_16(), where is simplifies the function. In fact, the pca957x_write_regs_16() now looks rather similar to pca953x_write_regs_24() and pca953x_write_regs_16(), which is intended for subsequent patches. Signed-off-by: Marek Vasut Cc: Linus Walleij Cc: Bartosz Golaszewski --- drivers/gpio/gpio-pca953x.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 4e9c79ca69c5..479fa376bd18 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -215,13 +215,10 @@ static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val) { - int ret; - - ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]); - if (ret < 0) - return ret; + u32 regaddr = (reg << 1) | REG_ADDR_AI; - return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]); + return i2c_smbus_write_i2c_block_data(chip->client, regaddr, + NBANK(chip), val); } static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val) @@ -408,6 +405,7 @@ static void pca953x_gpio_set_multiple(struct gpio_chip *gc, { struct pca953x_chip *chip = gpiochip_get_data(gc); int bank_shift = pca953x_bank_shift(chip); + u32 regaddr = chip->regs->output << bank_shift; unsigned int bank_mask, bank_val; int bank; u8 reg_val[MAX_BANK]; @@ -426,8 +424,13 @@ static void pca953x_gpio_set_multiple(struct gpio_chip *gc, } } - ret = i2c_smbus_write_i2c_block_data(chip->client, - chip->regs->output << bank_shift, + /* PCA9575 needs address-increment on multi-byte writes */ + if ((PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) && + (NBANK(chip) > 1)) { + regaddr |= REG_ADDR_AI; + } + + ret = i2c_smbus_write_i2c_block_data(chip->client, regaddr, NBANK(chip), reg_val); if (ret) goto exit;