[v4,10/10] Add RISC-V 32-bit target to build-many-glibcs.py

Message ID	858a04037082f99ac74766df696f6a7c9c986ada.1543572707.git.zongbox@gmail.com
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Headers	show Return-Path: <libc-alpha-return-97846-incoming=patchwork.ozlabs.org@sourceware.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=lw5zq2pInZHAQtOFqQ1r0KoRqNpW5Tw 7/Mb4q/b9u0WpdIPKs4E/9irEgdswN5m4gA0y4ry7dXb3x5Iscayhg+kyaW81wop cK7Ju7tX9ePqh7mI25s5s+PDX/ojQaouocB0xwaSrfCfoeZtlr1oWcMFh2FuwZ4A mIZcxrxtv+kA= Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk Sender: libc-alpha-owner@sourceware.org From: Zong Li <zongbox@gmail.com> To: joseph@codesourcery.com, palmer@dabbelt.com, darius@bluespec.com, andrew@sifive.com, dj@redhat.com, libc-alpha@sourceware.org Cc: zong@andestech.com, Zong Li <zongbox@gmail.com> Subject: [PATCH v4 10/10] Add RISC-V 32-bit target to build-many-glibcs.py Date: Sat, 1 Dec 2018 11:10:53 +0800 Message-Id: <858a04037082f99ac74766df696f6a7c9c986ada.1543572707.git.zongbox@gmail.com> In-Reply-To: <cover.1543572707.git.zongbox@gmail.com> References: <cover.1543572707.git.zongbox@gmail.com>
Series	RISC-V glibc port for the 32-bit \| expand [v4,00/10] RISC-V glibc port for the 32-bit [v4,01/10] Documentation for the RISC-V 32-bit port [v4,02/10] RISC-V: Support dynamic loader for the 32-bit [v4,03/10] RISC-V: Add path of library directories for the 32-bit [v4,04/10] RISC-V: The ABI implementation for the 32-bit [v4,05/10] RISC-V: Hard float support for the 32 bit [v4,06/10] RISC-V: Regenerate ULPs of RISC-V [v4,07/10] RISC-V: Add ABI lists [v4,08/10] RISC-V: Build Infastructure for the 32-bit [v4,09/10] RISC-V: Fix llrint and llround missing exceptions on RV32 [v4,10/10] Add RISC-V 32-bit target to build-many-glibcs.py

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	Zong Li <zongbox@gmail.com>
Subject: [PATCH v4 10/10] Add RISC-V 32-bit target to build-many-glibcs.py
Date: Sat,  1 Dec 2018 11:10:53 +0800
Message-Id: <858a04037082f99ac74766df696f6a7c9c986ada.1543572707.git.zongbox@gmail.com>
In-Reply-To: <cover.1543572707.git.zongbox@gmail.com>
References: <cover.1543572707.git.zongbox@gmail.com>

Series

RISC-V glibc port for the 32-bit | expand

Commit Message

Zong Li Dec. 1, 2018, 3:10 a.m. UTC

Support building three variant of 32 bit RISC-V glibc as follows:
- riscv32-linux-gnu-rv32imac-ilp32
- riscv32-linux-gnu-rv32imafdc-ilp32
- riscv32-linux-gnu-rv32imafdc-ilp32d

2018-11-29  Zong Li  <zong@andestech.com>

	* scripts/build-many-glibcs.py (Context): Add rv32 targets.
---
 ChangeLog                    |  1 +
 scripts/build-many-glibcs.py | 15 +++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/ChangeLog b/ChangeLog
index ee74249..c569cc3 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -43,6 +43,7 @@ 
 	* sysdeps/unix/sysv/linux/riscv/shlib-versions: Likewise.
 	* sysdeps/riscv/preconfigure: Likewise.
 	* sysdeps/riscv/rv32/fix-fp-int-convert-overflow.h: New file.
+	* scripts/build-many-glibcs.py (Context): Add rv32 targets.
 
 2018-11-28  Florian Weimer  <fweimer@redhat.com>
 
diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py
index 98acabc..e322696 100755
--- a/scripts/build-many-glibcs.py
+++ b/scripts/build-many-glibcs.py
@@ -320,6 +320,21 @@  class Context(object):
                         variant='e500v1',
                         gcc_cfg=['--disable-multilib', '--enable-secureplt',
                                  '--enable-obsolete'])
+        self.add_config(arch='riscv32',
+                        os_name='linux-gnu',
+                        variant='rv32imac-ilp32',
+                        gcc_cfg=['--with-arch=rv32imac', '--with-abi=ilp32',
+                                 '--disable-multilib'])
+        self.add_config(arch='riscv32',
+                        os_name='linux-gnu',
+                        variant='rv32imafdc-ilp32',
+                        gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32',
+                                 '--disable-multilib'])
+        self.add_config(arch='riscv32',
+                        os_name='linux-gnu',
+                        variant='rv32imafdc-ilp32d',
+                        gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32d',
+                                 '--disable-multilib'])
         self.add_config(arch='riscv64',
                         os_name='linux-gnu',
                         variant='rv64imac-lp64',

[v4,10/10] Add RISC-V 32-bit target to build-many-glibcs.py

Commit Message

Patch