From patchwork Thu Jun 16 09:04:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot] ARM: add marvell specific cache operation Date: Wed, 15 Jun 2011 23:04:19 -0000 From: Lei Wen X-Patchwork-Id: 100610 Message-Id: <1308215059-10368-1-git-send-email-leiwen@marvell.com> To: u-boot@lists.denx.de, Prafulla@marvell.com, Wadaskar@marvell.com, prafulla@marvell.com, adrian.wenl@gmail.com For Marvell sheeva 88SV331xV5 core, it has one special cache asm code to do the clean and valid in one line. Signed-off-by: Lei Wen --- arch/arm/lib/cache.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 30686fe..ae8f7e0 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -33,11 +33,15 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) arm1136_cache_flush(); #endif #ifdef CONFIG_ARM926EJS +#if defined(CONFIG_SHEEVA_88SV331xV5) + asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0)); +#else /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); #endif +#endif #ifdef CONFIG_OMAP34XX void v7_flush_cache_all(void);