From patchwork Thu Nov 29 12:42:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jose Abreu X-Patchwork-Id: 1005354 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Qz3TeRZB"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=synopsys.com header.i=@synopsys.com header.b="AKiWEwTt"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 435HHZ1M4wz9s3C for ; Thu, 29 Nov 2018 23:43:06 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=jfQMKdMuZj5za5PZM8mNSmR3WZmrm/H3XETomGKyYjE=; b=Qz3 TeRZBRoeBQ93FoanWqQE1Bynb1D/S12BrTdfisqEunq33+bdikayQKBpbdAFE/iVOVfiahpQnIL2W IYnTrPl6n7bNo/FJOjyJ4VE+OZ6iU+IhFZS/YipDz8wYFSkRnQ/1p4lSddTGNyyLRUBQc7raPfK4i YIdAf9UuQNokTjBLzuDb1UZn4hiktnfSIGSYW9zsm8U8R1ybeRH5MJ0b4xcDf8Z7oUhVUgLH++tXt Q7n8pYax43ljDnGseiNt1PJ4hoi8+OZ+2fXSaf5kSLkEUPzhVVIUNHvMx1Z5OLYPLcjAcVlVw5wCh zZmkJ7tol2fQwzl0+Dl09jJiq+Gwpiw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gSLep-0005h8-TI; Thu, 29 Nov 2018 12:43:03 +0000 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111] helo=smtprelay.synopsys.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gSLen-0005g3-3m for linux-snps-arc@lists.infradead.org; Thu, 29 Nov 2018 12:43:02 +0000 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id A284210C11A2; Thu, 29 Nov 2018 04:42:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1543495366; bh=iTliEgV6ReEmVDtiPNhclUVkpQAMjfk6hcnZD/hbnWU=; h=From:To:Cc:Subject:Date:From; b=AKiWEwTtI6Nn8rjxidEhtQNwdGJkQvVpqP1i0RWAbTefXbelbvjv1Iwk88Oi2q3Pw QkGmBZyhheFwCnuXY+IEOuDSzg51JBcMrLtC2Cy+cbB/3Q8B+rnXAKw8We3TPmhTW4 6xCF7+Es0lcNFyHqIMucCfpzH+mVBwMfA72mDnnzMC8Ddp3kSsspdL1aNUPlWDV0NI 6vNp31r7f3onvhAzlRIJA+vJqoHnA5gGXGmKQ8DHnK6ZSIruMLvOM1+qD6UFtSd5Ly XiX32L7x/OXT2BXv/eRWcuWO88M756SAUvT6IVwfIESAlxixh2G4da3Uz8kGtvajs1 tkJ+1yWXbIEsw== Received: from joabreu-VirtualBox.internal.synopsys.com (joabreu-e7440.internal.synopsys.com [10.107.19.26]) by mailhost.synopsys.com (Postfix) with ESMTP id 122925861; Thu, 29 Nov 2018 04:42:44 -0800 (PST) From: Jose Abreu To: linux-snps-arc@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARC: io.h: Implement reads{x}()/writes{x}() Date: Thu, 29 Nov 2018 12:42:22 +0000 Message-Id: X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181129_044301_156109_03A54F9B X-CRM114-Status: UNSURE ( 9.49 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [198.182.60.111 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jose Abreu , Joao Pinto , Vineet Gupta , Alexey Brodkin , Vitor Soares MIME-Version: 1.0 Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Some ARC CPU's do not support unaligned loads/stores. Currently, generic implementation of reads{b/w/l}()/writes{b/w/l}() is being used with ARC. This can lead to misfunction of some drivers as generic functions do a plain dereference of a pointer that can be unaligned. Let's use {get/put}_unaligned() helper instead of plain dereference of pointer in order to fix this. We do not implement readsq()/writesq() as we assume that only HS is a 64 Bit CPU and that it supports unaligned loads/stores. Signed-off-by: Jose Abreu Tested-by: Vitor Soares Cc: Vineet Gupta Cc: Alexey Brodkin Cc: Joao Pinto Cc: Vitor Soares --- arch/arc/include/asm/io.h | 48 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index c22b181e8206..ca42c84af042 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -12,6 +12,7 @@ #include #include #include +#include #ifdef CONFIG_ISA_ARCV2 #include @@ -94,6 +95,27 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) return w; } +#define __raw_readsx(t,f) \ +static inline void __raw_reads##f(const volatile void __iomem *addr, \ + void *buffer, unsigned int count) \ +{ \ + if (count) { \ + u##t *buf = buffer; \ +\ + do { \ + u##t x = __raw_read##f(addr); \ + put_unaligned(x, buf++); \ + } while (--count); \ + } \ +} + +#define __raw_readsb __raw_readsb +__raw_readsx(8, b); +#define __raw_readsw __raw_readsw +__raw_readsx(16, w); +#define __raw_readsl __raw_readsl +__raw_readsx(32, l); + #define __raw_writeb __raw_writeb static inline void __raw_writeb(u8 b, volatile void __iomem *addr) { @@ -126,6 +148,26 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) } +#define __raw_writesx(t,f) \ +static inline void __raw_writes##f(volatile void __iomem *addr, \ + const void *buffer, unsigned int count) \ +{ \ + if (count) { \ + const u##t *buf = buffer; \ +\ + do { \ + __raw_write##f(get_unaligned(buf++), addr); \ + } while (--count); \ + } \ +} + +#define __raw_writesb __raw_writesb +__raw_writesx(8, b); +#define __raw_writesw __raw_writesw +__raw_writesx(16, w); +#define __raw_writesl __raw_writesl +__raw_writesx(32, l); + /* * MMIO can also get buffered/optimized in micro-arch, so barriers needed * Based on ARM model for the typical use case @@ -141,10 +183,16 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) +#define readsb(p,d,l) ({ __raw_readsb(p,d,l); __iormb(); }) +#define readsw(p,d,l) ({ __raw_readsw(p,d,l); __iormb(); }) +#define readsl(p,d,l) ({ __raw_readsl(p,d,l); __iormb(); }) #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) +#define writesb(p,d,l) ({ __iowmb(); __raw_writesb(p,d,l); }) +#define writesw(p,d,l) ({ __iowmb(); __raw_writesw(p,d,l); }) +#define writesl(p,d,l) ({ __iowmb(); __raw_writesl(p,d,l); }) /* * Relaxed API for drivers which can handle barrier ordering themselves