From patchwork Wed Nov 28 11:02:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1004437 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 434dFZ0TSZz9ryk for ; Wed, 28 Nov 2018 22:09:06 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 434dFY68rwzDqfZ for ; Wed, 28 Nov 2018 22:09:05 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=hegdevasant@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 434d7Q3zLrzDqfK for ; Wed, 28 Nov 2018 22:03:46 +1100 (AEDT) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id wASAxKs1009773 for ; Wed, 28 Nov 2018 06:03:44 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2p1nc0u8pk-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 28 Nov 2018 06:03:44 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 28 Nov 2018 11:03:42 -0000 Received: from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194) by e06smtp01.uk.ibm.com (192.168.101.131) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 28 Nov 2018 11:03:40 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id wASB3d7w58982498 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Nov 2018 11:03:39 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 30915A405F; Wed, 28 Nov 2018 11:03:39 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 25794A4053; Wed, 28 Nov 2018 11:03:38 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.109.198.143]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 28 Nov 2018 11:03:37 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Wed, 28 Nov 2018 16:32:39 +0530 X-Mailer: git-send-email 2.14.3 In-Reply-To: <20181128110244.17664-1-hegdevasant@linux.vnet.ibm.com> References: <20181128110244.17664-1-hegdevasant@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18112811-4275-0000-0000-000002E7F0B3 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18112811-4276-0000-0000-000037F530A7 Message-Id: <20181128110244.17664-18-hegdevasant@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-11-28_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1811280100 Subject: [Skiboot] [PATCH v6 17/22] fadump: Add support to trigger memory preserving IPL on BMC system X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stewart@linux.vnet.ibm.com, hbathini@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" On FSP based system we call 'attn' instruction. FSP detects attention and initiates memory preserving IPL. On BMC system we have to call SBE S0 interrupt to initiate memory preserving IPL. This patch adds support to call SBE S0 interrupt in assert path. Sequence : - S0 interrupt on slave chip SBE - S0 interrupt on master chip SBE Note that this is hooked to ipmi_terminate path. We have HDAT flag for MPIPL support. If MPIPL is not supported then we don't create 'ibm,opal/dump' node and we will fall back to existing termination flow. Note: - It uses xscom node to detect master and slave chip. So that we can trigger early MPIPL (even before initializing SBE driver). - At present we do not have a proper way to detect SBE is alive or not. So we wait for predefined time and then call normal reboot. Signed-off-by: Vasant Hegde --- hw/ipmi/ipmi-attn.c | 4 ++++ hw/sbe-p9.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/sbe-p9.h | 10 +++++++++ 3 files changed, 76 insertions(+) diff --git a/hw/ipmi/ipmi-attn.c b/hw/ipmi/ipmi-attn.c index 8ff872c62..cf605feaf 100644 --- a/hw/ipmi/ipmi-attn.c +++ b/hw/ipmi/ipmi-attn.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +66,9 @@ static void ipmi_log_terminate_event(const char *msg) void __attribute__((noreturn)) ipmi_terminate(const char *msg) { + /* If MPIPL is supported then trigger SBE interrupt to initiate MPIPL */ + p9_sbe_terminate(); + /* Terminate called before initializing IPMI (early abort) */ if (!ipmi_present()) { if (platform.cec_reboot) diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c index c193ed075..924f73761 100644 --- a/hw/sbe-p9.c +++ b/hw/sbe-p9.c @@ -947,3 +947,65 @@ void p9_sbe_init(void) /* Initiate SBE timeout poller */ opal_add_poller(p9_sbe_timeout_poll, NULL); } + +/* Terminate and initiate MPIPL */ +void p9_sbe_terminate(void) +{ + uint32_t chip_id; + uint32_t primary_chip = -1; + int rc; + u64 wait_tb; + struct dt_node *xn; + + if (proc_gen < proc_gen_p9) + return; + + /* Return if MPIPL is not supported */ + if (!dt_find_by_path(opal_node, "dump")) + return; + + dt_for_each_compatible(dt_root, xn, "ibm,xscom") { + chip_id = dt_get_chip_id(xn); + + if (dt_has_node_property(xn, "primary", NULL)) { + primary_chip = chip_id; + continue; + } + + rc = xscom_write(chip_id, + SBE_CONTROL_REG_RW, SBE_CONTROL_REG_S0); + /* Initiate normal reboot */ + if (rc) { + prlog(PR_ERR, "Failed to write S0 interrupt [chip id = %x]\n", + chip_id); + return; + } + } + + if (primary_chip == -1) { + prlog(PR_ERR, "Master chip ID not found.\n"); + return; + } + + /* Write S0 interrupt on master SBE */ + rc = xscom_write(primary_chip, + SBE_CONTROL_REG_RW, SBE_CONTROL_REG_S0); + /* Initiate normal reboot */ + if (rc) { + prlog(PR_ERR, "Failed to write S0 interrupt [chip id = %x]\n", + primary_chip); + return; + } + + /* XXX We do not have a way to detect SBE state. Hence wait for max + * time SBE takes to respond and then trigger normal reboot. + */ + prlog(PR_DEBUG, "Initiated MPIPL, waiting for SBE to respond...\n"); + wait_tb = mftb() + msecs_to_tb(SBE_CMD_TIMEOUT_MAX); + while (mftb() < wait_tb) { + cpu_relax(); + } + prlog(PR_ERR, "SBE did not respond within timeout period (%d secs).\n", + SBE_CMD_TIMEOUT_MAX / 1000); + prlog(PR_ERR, "Falling back to normal reboot\n"); +} diff --git a/include/sbe-p9.h b/include/sbe-p9.h index 5f36cb39e..6a852edc2 100644 --- a/include/sbe-p9.h +++ b/include/sbe-p9.h @@ -103,6 +103,13 @@ #define SBE_HOST_TIMER_EXPIRY PPC_BIT(14) #define SBE_HOST_RESPONSE_MASK (PPC_BITMASK(0, 4) | SBE_HOST_TIMER_EXPIRY) +/* SBE Control Register */ +#define SBE_CONTROL_REG_RW 0x00050008 + +/* SBE interrupt s0/s1 bits */ +#define SBE_CONTROL_REG_S0 PPC_BIT(14) +#define SBE_CONTROL_REG_S1 PPC_BIT(15) + /* SBE Target Type */ #define SBE_TARGET_TYPE_PROC 0x00 #define SBE_TARGET_TYPE_EX 0x01 @@ -243,4 +250,7 @@ extern void p9_sbe_update_timer_expiry(uint64_t new_target); /* Send skiboot relocated base address to SBE */ extern void p9_sbe_send_relocated_base(uint64_t reloc_base); +/* Terminate and trigger MPIPL */ +extern void p9_sbe_terminate(void); + #endif /* __SBE_P9_H */