From patchwork Sun Nov 25 07:43:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 1002757 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kv3Xh1Hd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 432hsc3V8cz9s3C for ; Sun, 25 Nov 2018 18:45:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726810AbeKYSe2 (ORCPT ); Sun, 25 Nov 2018 13:34:28 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:39880 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727573AbeKYSe2 (ORCPT ); Sun, 25 Nov 2018 13:34:28 -0500 Received: by mail-wm1-f66.google.com with SMTP id u13-v6so15311010wmc.4; Sat, 24 Nov 2018 23:43:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=r1t1+K70MuQ6CIfy7Wgp1L7Kl8mx3XOTA4Vtxtq+eOs=; b=kv3Xh1HdQ7BPoBV56XO3W5TKrKMpFKWgX46s0zugdxCUMb7eJXuZthomI9uwuMh7J2 9IW8nbXDo1HQ/G1yw8T0IDHN7d643raQfx/j+7tgOM6AVaItyBwFAWogtaFYpi4fo8wB fxop5T+pU0Y3LJEH9OXkFDNjBWkG2Sdv8evYc9eJKnEQzpnoFfqvzl5G+Ta1ljXj5Yfv +2wzHvX9Dwl3MvwZnMg7UJ5aEscerfWtd+VRWGGR4Xu336P+ZU/YonD50XfxkskSgDej Elbcr8AzmMR9orK69KKkxiXppqzU10oNWJ+kFHYhk9viuOJmhM4tgnhY3XAd3s2ryN5n f43Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=r1t1+K70MuQ6CIfy7Wgp1L7Kl8mx3XOTA4Vtxtq+eOs=; b=Jh8mvWV8iiPED9lvOtAP7P57z0Q/iAiAke93+Nk0FZfBBFVs255l76lqCmbdxnRJCF Oq0hQ1N/xvGdr7zPawCDdhF8TEyLu4DKuZfp0HGLHzXo6mn+EsOSAcfJcO4RHsFRMnMD eSZ7/G7KaO49zfltgUacVCId+a85U7jh7IbM4dm20vMAISQF6MXMlSk62KkTPN+G9Xs4 kt6x0t/z+nv5ldTpSfPNSztrAO5lIF0pv1zodvBQJEBc+cmdWbHD4ML7JSEdu2UUqSKF 10Kb/1Xi1Gc0ukmClCL06dT0xYr3M5Endcj/BzMPRFVUO5MJ1Pc6vFizAIvVeh4ptWRm xGxA== X-Gm-Message-State: AGRZ1gK4S82Cmp2Hy14W8L/jTYNibjBEgWIzA141fRQt36lQWaI0WIwv 1zpioxW7PL4R7KgmbP9Z1xrtbhicJBA= X-Google-Smtp-Source: AJdET5c4Zqajrupn6z1eF0bRHaiePEngnhFgTPALCDwKdmY/qNKgrMSteBc1bwjNYy4fDw/HqKSE3w== X-Received: by 2002:a1c:b58b:: with SMTP id e133mr20180076wmf.0.1543131837991; Sat, 24 Nov 2018 23:43:57 -0800 (PST) Received: from localhost.localdomain ([185.219.177.224]) by smtp.gmail.com with ESMTPSA id 6-v6sm12296780wmg.19.2018.11.24.23.43.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 24 Nov 2018 23:43:57 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Mesih Kilinc , Maxime Ripard , Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby Subject: [RFC PATCH v4 07/17] irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s Date: Sun, 25 Nov 2018 10:43:10 +0300 Message-Id: <1f3cce09623052eaa90093f13ea9d13047a2b250.1543131714.git.mesihkilinc@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds support for suniv Allwinner ARMv5 F1C100s SoC which has stripped version of interrupt controller that found in A10/A13. Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard --- drivers/irqchip/irq-sun4i.c | 47 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c index 507f4e3..fb78d66 100644 --- a/drivers/irqchip/irq-sun4i.c +++ b/drivers/irqchip/irq-sun4i.c @@ -32,6 +32,8 @@ #define SUN4I_IRQ_MASK_REG(data, x) ((data)->mask_reg_offset + 0x4 * x) #define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40 #define SUN4I_IRQ_MASK_REG_OFFSET 0x50 +#define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20 +#define SUNIV_IRQ_MASK_REG_OFFSET 0x30 struct sun4i_irq_chip_data { void __iomem *irq_base; @@ -105,15 +107,6 @@ static const struct irq_domain_ops sun4i_irq_ops = { static int __init sun4i_of_init(struct device_node *node, struct device_node *parent) { - irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); - if (!irq_ic_data) { - pr_err("kzalloc failed!\n"); - return -ENOMEM; - } - - irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; - irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; - irq_ic_data->irq_base = of_iomap(node, 0); if (!irq_ic_data->irq_base) panic("%pOF: unable to map IC registers\n", @@ -149,7 +142,41 @@ static int __init sun4i_of_init(struct device_node *node, return 0; } -IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init); + +static int __init sun4i_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); + if (!irq_ic_data) { + pr_err("kzalloc failed!\n"); + return -ENOMEM; + } + + irq_ic_data->enable_reg_offset = SUN4I_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUN4I_IRQ_MASK_REG_OFFSET; + + return sun4i_of_init(node, parent); +} + +IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init); + +static int __init suniv_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + irq_ic_data = kzalloc(sizeof(struct sun4i_irq_chip_data), GFP_KERNEL); + if (!irq_ic_data) { + pr_err("kzalloc failed!\n"); + return -ENOMEM; + } + + irq_ic_data->enable_reg_offset = SUNIV_IRQ_ENABLE_REG_OFFSET; + irq_ic_data->mask_reg_offset = SUNIV_IRQ_MASK_REG_OFFSET; + + return sun4i_of_init(node, parent); +} + +IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic", + suniv_ic_of_init); static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs) {