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[U-Boot,v4,11/28] riscv: complete the list of exception codes

Message ID 20181122102637.17361-12-lukas.auer@aisec.fraunhofer.de
State Accepted
Delegated to: Andes
Headers show
Series General fixes / cleanup for RISC-V and improvements to qemu-riscv | expand

Commit Message

Lukas Auer Nov. 22, 2018, 10:26 a.m. UTC 
Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/riscv/lib/interrupts.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)
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Patch

diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 62a16b4da9..6a12818c2b 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -67,7 +67,18 @@  static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
 		"Instruction access fault",
 		"Illegal instruction",
 		"Breakpoint",
-		"Load address misaligned"
+		"Load address misaligned",
+		"Load access fault",
+		"Store/AMO address misaligned",
+		"Store/AMO access fault",
+		"Environment call from U-mode",
+		"Environment call from S-mode",
+		"Reserved",
+		"Environment call from M-mode",
+		"Instruction page fault",
+		"Load page fault",
+		"Reserved",
+		"Store/AMO page fault",
 	};
 
 	printf("exception code: %ld , %s , epc %lx , ra %lx\n",