[U-Boot,v4,02/28] dts: riscv: update makefile to also clean the RISC-V dts directory

From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
To: <u-boot@lists.denx.de>
Date: Thu, 22 Nov 2018 11:26:11 +0100
Message-ID: <20181122102637.17361-3-lukas.auer@aisec.fraunhofer.de>
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Subject: [U-Boot] [PATCH v4 02/28] dts: riscv: update makefile to also clean
	the RISC-V dts directory
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Message ID	20181122102637.17361-3-lukas.auer@aisec.fraunhofer.de
State	Accepted
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> To: <u-boot@lists.denx.de> Date: Thu, 22 Nov 2018 11:26:11 +0100 Message-ID: <20181122102637.17361-3-lukas.auer@aisec.fraunhofer.de> In-Reply-To: <20181122102637.17361-1-lukas.auer@aisec.fraunhofer.de> References: <20181122102637.17361-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v4 02/28] dts: riscv: update makefile to also clean the RISC-V dts directory Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	General fixes / cleanup for RISC-V and improvements to qemu-riscv \| expand [U-Boot,v4,00/28] General fixes / cleanup for RISC-V and improvements to qemu-riscv [U-Boot,v4,01/28] tools: .gitignore: add prelink-riscv [U-Boot,v4,02/28] dts: riscv: update makefile to also clean the RISC-V dts directory [U-Boot,v4,03/28] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I [U-Boot,v4,04/28] riscv: select CONFIG_PHYS_64BIT on RV64I systems [U-Boot,v4,05/28] riscv: add Kconfig entries for the C and A ISA extensions [U-Boot,v4,06/28] riscv: set -march and -mabi based on the Kconfig configuration [U-Boot,v4,07/28] riscv: enable -fdata-sections [U-Boot,v4,08/28] riscv: fix use of incorrectly sized variables [U-Boot,v4,09/28] riscv: make use of the barrier functions from Linux [U-Boot,v4,10/28] riscv: do not reimplement generic io functions [U-Boot,v4,11/28] riscv: complete the list of exception codes [U-Boot,v4,12/28] riscv: treat undefined exception codes as reserved [U-Boot,v4,13/28] riscv: hang on unhandled exceptions [U-Boot,v4,14/28] riscv: implement the invalidate_icache_* functions [U-Boot,v4,15/28] riscv: fix inconsistent use of spaces and tabs in start.S [U-Boot,v4,16/28] riscv: align mtvec on a 4-byte boundary [U-Boot,v4,17/28] Drop CONFIG_INIT_CRITICAL [U-Boot,v4,18/28] riscv: remove unused labels in start.S [U-Boot,v4,19/28] riscv: do not blindly modify the mstatus CSR [U-Boot,v4,20/28] riscv: save hart ID and device tree passed by prior boot stage [U-Boot,v4,21/28] riscv: qemu: use device tree passed by prior boot stage [U-Boot,v4,22/28] riscv: qemu: support booting Linux [U-Boot,v4,23/28] riscv: align bootm implementation with that of other architectures [U-Boot,v4,24/28] distro_bootcmd: add VirtIO distro boot command [U-Boot,v4,25/28] riscv: qemu: enable distro boot [U-Boot,v4,26/28] dm: core: add missing prototype for ofnode_read_u64 [U-Boot,v4,27/28] riscv: qemu: detect and boot the kernel passed by QEMU [U-Boot,v4,28/28] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL

[U-Boot,v4,02/28] dts: riscv: update makefile to also clean the RISC-V dts directory

Commit Message

Patch