Message ID | 4DF4E053.7050205@freebsd.org |
---|---|
State | New |
Headers | show |
On 12.06.2011, at 17:50, Nathan Whitehorn wrote: > The PIR register is architecturally specified on all PowerPC non-embedded CPUs, but currently is only available on the 604, 620, and G4. Add it to all 601-derived CPUs. Looking through the respective specs, I found the following matrix on PIR support: 601 yes 603e ? (no) 604e yes 750 ? (no) 7540 yes 970 yes 601 and 750 user manuals don't mention PIR. The overall 32-bit microarchitecture states PIR as "optional". So I'd say 750 and 603 simply don't implement it. However, that means it's missing for 970 and 601. Could you please update your patch accordingly? Alex > > Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org> > --- > target-ppc/translate_init.c | 20 +++++--------------- > 1 files changed, 5 insertions(+), 15 deletions(-) > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index b511afa..1286ddf 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -670,6 +670,11 @@ static void gen_spr_ne_601 (CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_sdr1, > 0x00000000); > + /* Processor identification */ > + spr_register(env, SPR_PIR, "PIR", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_pir, > + env->cpu_index); > } > > /* BATs 0-3 */ > @@ -1019,11 +1024,6 @@ static void gen_spr_thrm (CPUPPCState *env) > /* SPR specific to PowerPC 604 implementation */ > static void gen_spr_604 (CPUPPCState *env) > { > - /* Processor identification */ > - spr_register(env, SPR_PIR, "PIR", > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_pir, > - 0x00000000); > /* Breakpoints */ > /* XXX : not implemented */ > spr_register(env, SPR_IABR, "IABR", > @@ -1259,11 +1259,6 @@ static void gen_spr_601 (CPUPPCState *env) > > static void gen_spr_74xx (CPUPPCState *env) > { > - /* Processor identification */ > - spr_register(env, SPR_PIR, "PIR", > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_pir, > - 0x00000000); > /* XXX : not implemented */ > spr_register(env, SPR_MMCR2, "MMCR2", > SPR_NOACCESS, SPR_NOACCESS, > @@ -2118,11 +2113,6 @@ static void gen_spr_compress (CPUPPCState *env) > /* SPR specific to PowerPC 620 */ > static void gen_spr_620 (CPUPPCState *env) > { > - /* Processor identification */ > - spr_register(env, SPR_PIR, "PIR", > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_pir, > - 0x00000000); > spr_register(env, SPR_ASR, "ASR", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_asr, &spr_write_asr, >
On 04.07.2011, at 17:43, Nathan Whitehorn wrote: > On 07/04/11 10:21, Alexander Graf wrote: >> On 12.06.2011, at 17:50, Nathan Whitehorn wrote: >> >>> The PIR register is architecturally specified on all PowerPC non-embedded CPUs, but currently is only available on the 604, 620, and G4. Add it to all 601-derived CPUs. >> Looking through the respective specs, I found the following matrix on PIR support: >> >> 601 yes >> 603e ? (no) >> 604e yes >> 750 ? (no) >> 7540 yes >> 970 yes >> >> 601 and 750 user manuals don't mention PIR. The overall 32-bit microarchitecture states PIR as "optional". So I'd say 750 and 603 simply don't implement it. However, that means it's missing for 970 and 601. Could you please update your patch accordingly? > > The actual 750 next to my desk has it, at least, but Freescale claims the 603 doesn't. Should I update it for all of the individual CPUs, then, instead of the 6xx patch? If you have actual hardware to verify against, I'd say that overrules specs. But yes, please update it for the individual CPUs :). Alex PS: Please always reply-to-all on mailing list mails unless there's a very good reason not to (personal, nda, ...).
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index b511afa..1286ddf 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -670,6 +670,11 @@ static void gen_spr_ne_601 (CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_sdr1, 0x00000000); + /* Processor identification */ + spr_register(env, SPR_PIR, "PIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pir, + env->cpu_index); } /* BATs 0-3 */ @@ -1019,11 +1024,6 @@ static void gen_spr_thrm (CPUPPCState *env) /* SPR specific to PowerPC 604 implementation */ static void gen_spr_604 (CPUPPCState *env) { - /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); /* Breakpoints */ /* XXX : not implemented */ spr_register(env, SPR_IABR, "IABR", @@ -1259,11 +1259,6 @@ static void gen_spr_601 (CPUPPCState *env) static void gen_spr_74xx (CPUPPCState *env) { - /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); /* XXX : not implemented */ spr_register(env, SPR_MMCR2, "MMCR2", SPR_NOACCESS, SPR_NOACCESS, @@ -2118,11 +2113,6 @@ static void gen_spr_compress (CPUPPCState *env) /* SPR specific to PowerPC 620 */ static void gen_spr_620 (CPUPPCState *env) { - /* Processor identification */ - spr_register(env, SPR_PIR, "PIR", - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_pir, - 0x00000000); spr_register(env, SPR_ASR, "ASR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_asr, &spr_write_asr,
The PIR register is architecturally specified on all PowerPC non-embedded CPUs, but currently is only available on the 604, 620, and G4. Add it to all 601-derived CPUs. Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org> --- target-ppc/translate_init.c | 20 +++++--------------- 1 files changed, 5 insertions(+), 15 deletions(-)