| Message ID | 20181002161915.18843-1-richard.henderson@linaro.org |
|---|---|
| Headers | show |
| Series | LSE atomics out-of-line | expand |
Ping. On 10/2/18 9:19 AM, Richard Henderson wrote: > Changes since v1: > * Use config/t-slibgcc-libgcc instead of gcc.c changes. > * Some style fixes. > * Ifdefs to work with old glibc. > > * Force TImode registers into even regnos. > Required by CASP, allowed by the ABI, and is seen as the > simplier solution than adding two new register classes. > > * Use match_dup instead of matching constraints for CAS{P}. > Matching constraints result in lots of extraneous moves > for TImode, and keeping the expander interface the same > for non-TImode simplifies the code. > > > r~ > > > Richard Henderson (11): > aarch64: Simplify LSE cas generation > aarch64: Improve cas generation > aarch64: Improve swp generation > aarch64: Improve atomic-op lse generation > aarch64: Emit LSE st<op> instructions > Add visibility to libfunc constructors > aarch64: Add out-of-line functions for LSE atomics > aarch64: Implement -matomic-ool > aarch64: Force TImode values into even registers > aarch64: Implement TImode compare-and-swap > Enable -matomic-ool by default > > gcc/config/aarch64/aarch64-protos.h | 20 +- > gcc/optabs-libfuncs.h | 2 + > gcc/common/config/aarch64/aarch64-common.c | 6 +- > gcc/config/aarch64/aarch64.c | 494 +++++++------- > gcc/optabs-libfuncs.c | 26 +- > .../atomic-comp-swap-release-acquire.c | 2 +- > .../gcc.target/aarch64/atomic-inst-ldadd.c | 18 +- > .../gcc.target/aarch64/atomic-inst-ldlogic.c | 54 +- > .../gcc.target/aarch64/atomic-op-acq_rel.c | 2 +- > .../gcc.target/aarch64/atomic-op-acquire.c | 2 +- > .../gcc.target/aarch64/atomic-op-char.c | 2 +- > .../gcc.target/aarch64/atomic-op-consume.c | 2 +- > .../gcc.target/aarch64/atomic-op-imm.c | 2 +- > .../gcc.target/aarch64/atomic-op-int.c | 2 +- > .../gcc.target/aarch64/atomic-op-long.c | 2 +- > .../gcc.target/aarch64/atomic-op-relaxed.c | 2 +- > .../gcc.target/aarch64/atomic-op-release.c | 2 +- > .../gcc.target/aarch64/atomic-op-seq_cst.c | 2 +- > .../gcc.target/aarch64/atomic-op-short.c | 2 +- > .../aarch64/atomic_cmp_exchange_zero_reg_1.c | 2 +- > .../atomic_cmp_exchange_zero_strong_1.c | 2 +- > .../gcc.target/aarch64/sync-comp-swap.c | 2 +- > .../gcc.target/aarch64/sync-op-acquire.c | 2 +- > .../gcc.target/aarch64/sync-op-full.c | 2 +- > libgcc/config/aarch64/lse.c | 282 ++++++++ > gcc/config/aarch64/aarch64.opt | 4 + > gcc/config/aarch64/atomics.md | 608 ++++++++++-------- > gcc/config/aarch64/iterators.md | 8 +- > gcc/config/aarch64/predicates.md | 12 + > gcc/doc/invoke.texi | 14 +- > libgcc/config.host | 4 + > libgcc/config/aarch64/t-lse | 48 ++ > 32 files changed, 1058 insertions(+), 576 deletions(-) > create mode 100644 libgcc/config/aarch64/lse.c > create mode 100644 libgcc/config/aarch64/t-lse >
Ping 2. On 10/11/18 6:33 PM, Richard Henderson wrote: > Ping. > > On 10/2/18 9:19 AM, Richard Henderson wrote: >> Changes since v1: >> * Use config/t-slibgcc-libgcc instead of gcc.c changes. >> * Some style fixes. >> * Ifdefs to work with old glibc. >> >> * Force TImode registers into even regnos. >> Required by CASP, allowed by the ABI, and is seen as the >> simplier solution than adding two new register classes. >> >> * Use match_dup instead of matching constraints for CAS{P}. >> Matching constraints result in lots of extraneous moves >> for TImode, and keeping the expander interface the same >> for non-TImode simplifies the code. >> >> >> r~ >> >> >> Richard Henderson (11): >> aarch64: Simplify LSE cas generation >> aarch64: Improve cas generation >> aarch64: Improve swp generation >> aarch64: Improve atomic-op lse generation >> aarch64: Emit LSE st<op> instructions >> Add visibility to libfunc constructors >> aarch64: Add out-of-line functions for LSE atomics >> aarch64: Implement -matomic-ool >> aarch64: Force TImode values into even registers >> aarch64: Implement TImode compare-and-swap >> Enable -matomic-ool by default >> >> gcc/config/aarch64/aarch64-protos.h | 20 +- >> gcc/optabs-libfuncs.h | 2 + >> gcc/common/config/aarch64/aarch64-common.c | 6 +- >> gcc/config/aarch64/aarch64.c | 494 +++++++------- >> gcc/optabs-libfuncs.c | 26 +- >> .../atomic-comp-swap-release-acquire.c | 2 +- >> .../gcc.target/aarch64/atomic-inst-ldadd.c | 18 +- >> .../gcc.target/aarch64/atomic-inst-ldlogic.c | 54 +- >> .../gcc.target/aarch64/atomic-op-acq_rel.c | 2 +- >> .../gcc.target/aarch64/atomic-op-acquire.c | 2 +- >> .../gcc.target/aarch64/atomic-op-char.c | 2 +- >> .../gcc.target/aarch64/atomic-op-consume.c | 2 +- >> .../gcc.target/aarch64/atomic-op-imm.c | 2 +- >> .../gcc.target/aarch64/atomic-op-int.c | 2 +- >> .../gcc.target/aarch64/atomic-op-long.c | 2 +- >> .../gcc.target/aarch64/atomic-op-relaxed.c | 2 +- >> .../gcc.target/aarch64/atomic-op-release.c | 2 +- >> .../gcc.target/aarch64/atomic-op-seq_cst.c | 2 +- >> .../gcc.target/aarch64/atomic-op-short.c | 2 +- >> .../aarch64/atomic_cmp_exchange_zero_reg_1.c | 2 +- >> .../atomic_cmp_exchange_zero_strong_1.c | 2 +- >> .../gcc.target/aarch64/sync-comp-swap.c | 2 +- >> .../gcc.target/aarch64/sync-op-acquire.c | 2 +- >> .../gcc.target/aarch64/sync-op-full.c | 2 +- >> libgcc/config/aarch64/lse.c | 282 ++++++++ >> gcc/config/aarch64/aarch64.opt | 4 + >> gcc/config/aarch64/atomics.md | 608 ++++++++++-------- >> gcc/config/aarch64/iterators.md | 8 +- >> gcc/config/aarch64/predicates.md | 12 + >> gcc/doc/invoke.texi | 14 +- >> libgcc/config.host | 4 + >> libgcc/config/aarch64/t-lse | 48 ++ >> 32 files changed, 1058 insertions(+), 576 deletions(-) >> create mode 100644 libgcc/config/aarch64/lse.c >> create mode 100644 libgcc/config/aarch64/t-lse >>
Changes since v1: * Use config/t-slibgcc-libgcc instead of gcc.c changes. * Some style fixes. * Ifdefs to work with old glibc. * Force TImode registers into even regnos. Required by CASP, allowed by the ABI, and is seen as the simplier solution than adding two new register classes. * Use match_dup instead of matching constraints for CAS{P}. Matching constraints result in lots of extraneous moves for TImode, and keeping the expander interface the same for non-TImode simplifies the code. r~ Richard Henderson (11): aarch64: Simplify LSE cas generation aarch64: Improve cas generation aarch64: Improve swp generation aarch64: Improve atomic-op lse generation aarch64: Emit LSE st<op> instructions Add visibility to libfunc constructors aarch64: Add out-of-line functions for LSE atomics aarch64: Implement -matomic-ool aarch64: Force TImode values into even registers aarch64: Implement TImode compare-and-swap Enable -matomic-ool by default gcc/config/aarch64/aarch64-protos.h | 20 +- gcc/optabs-libfuncs.h | 2 + gcc/common/config/aarch64/aarch64-common.c | 6 +- gcc/config/aarch64/aarch64.c | 494 +++++++------- gcc/optabs-libfuncs.c | 26 +- .../atomic-comp-swap-release-acquire.c | 2 +- .../gcc.target/aarch64/atomic-inst-ldadd.c | 18 +- .../gcc.target/aarch64/atomic-inst-ldlogic.c | 54 +- .../gcc.target/aarch64/atomic-op-acq_rel.c | 2 +- .../gcc.target/aarch64/atomic-op-acquire.c | 2 +- .../gcc.target/aarch64/atomic-op-char.c | 2 +- .../gcc.target/aarch64/atomic-op-consume.c | 2 +- .../gcc.target/aarch64/atomic-op-imm.c | 2 +- .../gcc.target/aarch64/atomic-op-int.c | 2 +- .../gcc.target/aarch64/atomic-op-long.c | 2 +- .../gcc.target/aarch64/atomic-op-relaxed.c | 2 +- .../gcc.target/aarch64/atomic-op-release.c | 2 +- .../gcc.target/aarch64/atomic-op-seq_cst.c | 2 +- .../gcc.target/aarch64/atomic-op-short.c | 2 +- .../aarch64/atomic_cmp_exchange_zero_reg_1.c | 2 +- .../atomic_cmp_exchange_zero_strong_1.c | 2 +- .../gcc.target/aarch64/sync-comp-swap.c | 2 +- .../gcc.target/aarch64/sync-op-acquire.c | 2 +- .../gcc.target/aarch64/sync-op-full.c | 2 +- libgcc/config/aarch64/lse.c | 282 ++++++++ gcc/config/aarch64/aarch64.opt | 4 + gcc/config/aarch64/atomics.md | 608 ++++++++++-------- gcc/config/aarch64/iterators.md | 8 +- gcc/config/aarch64/predicates.md | 12 + gcc/doc/invoke.texi | 14 +- libgcc/config.host | 4 + libgcc/config/aarch64/t-lse | 48 ++ 32 files changed, 1058 insertions(+), 576 deletions(-) create mode 100644 libgcc/config/aarch64/lse.c create mode 100644 libgcc/config/aarch64/t-lse