| Message ID | cover.1535462942.git.amit.kucheria@linaro.org |
|---|---|
| Headers | show |
| Series | Another round of tsens cleanups | expand |
On Tue 28 Aug 06:38 PDT 2018, Amit Kucheria wrote: > We've earlier added support to split the register address space into TM > and SROT regions. > > Split up the regmap address space into two for the remaining platforms > that have a similar register layout and make corresponding changes to > the get_temp_common() function used by these platforms. > > Since tsens-common.c/init_common() currently only registers one address > space, the order is important (TM before SROT). This is OK since the > code doesn't really use the SROT functionality yet. > Having a single patch touching both code and dts will cause merge issues as this patch travel upstream. Even more arm-soc expects arm and arm64 dts changes to come in different pull requests. Please split it so that the three pieces can be picked up by respective maintainer. > Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- > arch/arm/boot/dts/qcom-msm8974.dtsi | 5 +++-- > arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- > drivers/thermal/qcom/tsens-common.c | 5 +++-- > 3 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi > index d9019a49b292..56dbbf788d15 100644 > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi > @@ -427,9 +427,10 @@ > }; > }; > > - tsens: thermal-sensor@fc4a8000 { > + tsens: thermal-sensor@fc4a9000 { > compatible = "qcom,msm8974-tsens"; > - reg = <0xfc4a8000 0x2000>; > + reg = <0xfc4a9000 0x1000>, /* TM */ > + <0xfc4a8000 0x1000>; /* SROT */ > nvmem-cells = <&tsens_calib>, <&tsens_backup>; > nvmem-cell-names = "calib", "calib_backup"; > #thermal-sensor-cells = <1>; > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 7b32b8990d62..6a277fce3333 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -761,9 +761,10 @@ > }; > }; > > - tsens: thermal-sensor@4a8000 { > + tsens: thermal-sensor@4a9000 { > compatible = "qcom,msm8916-tsens"; > - reg = <0x4a8000 0x2000>; > + reg = <0x4a9000 0x1000>, /* TM */ > + <0x4a8000 0x1000>; /* SROT */ > nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; > nvmem-cell-names = "calib", "calib_sel"; > #thermal-sensor-cells = <1>; > diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c > index 6207d8d92351..478739543bbc 100644 > --- a/drivers/thermal/qcom/tsens-common.c > +++ b/drivers/thermal/qcom/tsens-common.c > @@ -21,7 +21,7 @@ > #include <linux/regmap.h> > #include "tsens.h" > > -#define S0_ST_ADDR 0x1030 > +#define STATUS_OFFSET 0x30 > #define SN_ADDR_OFFSET 0x4 > #define SN_ST_TEMP_MASK 0x3ff > #define CAL_DEGC_PT1 30 > @@ -107,8 +107,9 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp) > unsigned int status_reg; > int last_temp = 0, ret; > > - status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET; > + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * SN_ADDR_OFFSET; Wasn't this change part of the previous set that introduced the tm_offset? If not how did we handle the fact that tmdev->map is already indented 0x1000 bytes? Both changes looks good, but I'm worries about the order of things. Regards, Bjorn > ret = regmap_read(tmdev->map, status_reg, &code); > + > if (ret) > return ret; > last_temp = code & SN_ST_TEMP_MASK; > -- > 2.17.1 >
On Tue 28 Aug 06:38 PDT 2018, Amit Kucheria wrote: > This new property allows the number of sensors to be configured from DT > instead of being hardcoded in platform data. Use it. > > Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Please split in arm and arm64. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > --- > arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + > arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi > index 56dbbf788d15..3c4b81c29798 100644 > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi > @@ -433,6 +433,7 @@ > <0xfc4a8000 0x1000>; /* SROT */ > nvmem-cells = <&tsens_calib>, <&tsens_backup>; > nvmem-cell-names = "calib", "calib_backup"; > + #qcom,sensors = <11>; > #thermal-sensor-cells = <1>; > }; > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > index 6a277fce3333..be27d8dc9e6b 100644 > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > @@ -767,6 +767,7 @@ > <0x4a8000 0x1000>; /* SROT */ > nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; > nvmem-cell-names = "calib", "calib_sel"; > + #qcom,sensors = <5>; > #thermal-sensor-cells = <1>; > }; > > -- > 2.17.1 >
On Tue 28 Aug 06:38 PDT 2018, Amit Kucheria wrote: > Instead of showing up as thermal-sensor@<addr>, the nodes will show up as > tsens0_tm, tsen1_tm, tsens1_srot, etc. in /proc/iomem making it easier to > read. > > IOW, > > 0c222000-0c2221fe : thermal-sensor@c263000 > 0c223000-0c2231fe : thermal-sensor@c265000 > 0c263000-0c2631fe : thermal-sensor@c263000 > 0c265000-0c2651fe : thermal-sensor@c265000 > > becomes > > 0c222000-0c2221fe : tsens0_srot > 0c223000-0c2231fe : tsens1_srot > 0c263000-0c2631fe : tsens0_tm > 0c265000-0c2651fe : tsens1_tm > > Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > --- > arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + > arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + > arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 ++ > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ > 4 files changed, 6 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi > index 3c4b81c29798..64c9f81ddd90 100644 > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi > @@ -431,6 +431,7 @@ > compatible = "qcom,msm8974-tsens"; > reg = <0xfc4a9000 0x1000>, /* TM */ > <0xfc4a8000 0x1000>; /* SROT */ > + reg-names = "tsens_tm", "tsens_srot"; While the iomem output seems more convenient this way, these register names are a contract between the DT binding and the particular tsens instance. As such this is a good idea, but with the names should not include the instance information. They should be "tm", "srot". > nvmem-cells = <&tsens_calib>, <&tsens_backup>; > nvmem-cell-names = "calib", "calib_backup"; > #qcom,sensors = <11>; [..] > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > index 0c9a2aa6a1b5..f1a36d6829cf 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -966,6 +966,7 @@ > compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; > reg = <0xc263000 0x1ff>, /* TM */ > <0xc222000 0x1ff>; /* SROT */ > + reg-names = "tsens0_tm", "tsens0_srot"; > #qcom,sensors = <13>; > #thermal-sensor-cells = <1>; > }; > @@ -974,6 +975,7 @@ > compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; > reg = <0xc265000 0x1ff>, /* TM */ > <0xc223000 0x1ff>; /* SROT */ > + reg-names = "tsens1_tm", "tsens1_srot"; And I do recognize that in this case iomem won't show which one is tsens0 and which is tsens1... As with previous patches, please split arm and arm64 in separate patches. Regards, Bjorn
Hi, On Mon, Sep 3, 2018 at 1:34 PM, Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > On Tue 28 Aug 06:38 PDT 2018, Amit Kucheria wrote: > >> Instead of showing up as thermal-sensor@<addr>, the nodes will show up as >> tsens0_tm, tsen1_tm, tsens1_srot, etc. in /proc/iomem making it easier to >> read. >> >> IOW, >> >> 0c222000-0c2221fe : thermal-sensor@c263000 >> 0c223000-0c2231fe : thermal-sensor@c265000 >> 0c263000-0c2631fe : thermal-sensor@c263000 >> 0c265000-0c2651fe : thermal-sensor@c265000 >> >> becomes >> >> 0c222000-0c2221fe : tsens0_srot >> 0c223000-0c2231fe : tsens1_srot >> 0c263000-0c2631fe : tsens0_tm >> 0c265000-0c2651fe : tsens1_tm >> >> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> >> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> >> --- >> arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + >> arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 + >> arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 ++ >> arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ >> 4 files changed, 6 insertions(+) >> >> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi >> index 3c4b81c29798..64c9f81ddd90 100644 >> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi >> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi >> @@ -431,6 +431,7 @@ >> compatible = "qcom,msm8974-tsens"; >> reg = <0xfc4a9000 0x1000>, /* TM */ >> <0xfc4a8000 0x1000>; /* SROT */ >> + reg-names = "tsens_tm", "tsens_srot"; > > While the iomem output seems more convenient this way, these register > names are a contract between the DT binding and the particular tsens > instance. > > As such this is a good idea, but with the names should not include the > instance information. They should be "tm", "srot". Rob Herring doesn't seem to think so. As per <http://lkml.kernel.org/r/CAL_Jsq+MMunmVWqeW9v2RyzsMKP+=kMzeTHNMG4JDHM7Fy0HBg@mail.gmail.com> I said: > From what you're saying the _only_ reason you'd ever want to use > reg-names is if there is an optional register range. Is that right? Rob said: > IMO, yes. It sounds like Rob won't NAK a change that adds reg-names if there is more than one reg, but in general he's not a fan. I'd vote to keep things consistent with Rob's worldview and just drop this change. -Doug
On Tue, Sep 4, 2018 at 1:29 AM Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > On Tue 28 Aug 06:38 PDT 2018, Amit Kucheria wrote: > > > We've earlier added support to split the register address space into TM > > and SROT regions. > > > > Split up the regmap address space into two for the remaining platforms > > that have a similar register layout and make corresponding changes to > > the get_temp_common() function used by these platforms. > > > > Since tsens-common.c/init_common() currently only registers one address > > space, the order is important (TM before SROT). This is OK since the > > code doesn't really use the SROT functionality yet. > > > > Having a single patch touching both code and dts will cause merge issues > as this patch travel upstream. Even more arm-soc expects arm and arm64 > dts changes to come in different pull requests. > Please split it so that the three pieces can be picked up by respective > maintainer. Will do. > > Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> > > Reviewed-by: Matthias Kaehlcke <mka@chromium.org> > > --- > > arch/arm/boot/dts/qcom-msm8974.dtsi | 5 +++-- > > arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- > > drivers/thermal/qcom/tsens-common.c | 5 +++-- > > 3 files changed, 9 insertions(+), 6 deletions(-) > > > > diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi > > index d9019a49b292..56dbbf788d15 100644 > > --- a/arch/arm/boot/dts/qcom-msm8974.dtsi > > +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi > > @@ -427,9 +427,10 @@ > > }; > > }; > > > > - tsens: thermal-sensor@fc4a8000 { > > + tsens: thermal-sensor@fc4a9000 { > > compatible = "qcom,msm8974-tsens"; > > - reg = <0xfc4a8000 0x2000>; > > + reg = <0xfc4a9000 0x1000>, /* TM */ > > + <0xfc4a8000 0x1000>; /* SROT */ > > nvmem-cells = <&tsens_calib>, <&tsens_backup>; > > nvmem-cell-names = "calib", "calib_backup"; > > #thermal-sensor-cells = <1>; > > diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > index 7b32b8990d62..6a277fce3333 100644 > > --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi > > +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi > > @@ -761,9 +761,10 @@ > > }; > > }; > > > > - tsens: thermal-sensor@4a8000 { > > + tsens: thermal-sensor@4a9000 { > > compatible = "qcom,msm8916-tsens"; > > - reg = <0x4a8000 0x2000>; > > + reg = <0x4a9000 0x1000>, /* TM */ > > + <0x4a8000 0x1000>; /* SROT */ > > nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; > > nvmem-cell-names = "calib", "calib_sel"; > > #thermal-sensor-cells = <1>; > > diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c > > index 6207d8d92351..478739543bbc 100644 > > --- a/drivers/thermal/qcom/tsens-common.c > > +++ b/drivers/thermal/qcom/tsens-common.c > > @@ -21,7 +21,7 @@ > > #include <linux/regmap.h> > > #include "tsens.h" > > > > -#define S0_ST_ADDR 0x1030 > > +#define STATUS_OFFSET 0x30 > > #define SN_ADDR_OFFSET 0x4 > > #define SN_ST_TEMP_MASK 0x3ff > > #define CAL_DEGC_PT1 30 > > @@ -107,8 +107,9 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp) > > unsigned int status_reg; > > int last_temp = 0, ret; > > > > - status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET; > > + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * SN_ADDR_OFFSET; > > Wasn't this change part of the previous set that introduced the > tm_offset? If not how did we handle the fact that tmdev->map is already > indented 0x1000 bytes? It was a similar change 5b1283984fa3 ("thermal: tsens: Add support to split up register address space into two") for the get_temp_8996() function. This patch converts over the remaining users. > Both changes looks good, but I'm worries about the order of things. We're OK.