| Message ID | 20180810173941.5301-1-cota@braap.org |
|---|---|
| Headers | show |
| Series | target/riscv: use tcg_lookup_and_goto_ptr | expand |
On Fri, Aug 10, 2018 at 13:39:38 -0400, Emilio G. Cota wrote: > Changes wrt v1: changed patch 3 as suggested by Richard. Also > added his R-b's. > > You can fetch this series from: > https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2 RISC-V maintainers: any plans of picking this up for 3.1? (Cc'ing Alistair since he recently submitted some riscv-related pull requests; BTW Alistair, should you be listed as a RISC-V maintainer?) Thanks, Emilio
On Fri, Aug 31, 2018 at 3:22 PM, Emilio G. Cota <cota@braap.org> wrote: > On Fri, Aug 10, 2018 at 13:39:38 -0400, Emilio G. Cota wrote: >> Changes wrt v1: changed patch 3 as suggested by Richard. Also >> added his R-b's. >> >> You can fetch this series from: >> https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2 > > RISC-V maintainers: any plans of picking this up for 3.1? Thanks for CCing me. I think Michael must be really busy, I haven't seen any activity for awhile. I'm going to send a PR with everything that has been reviewed and applies cleanly. Alistair > > (Cc'ing Alistair since he recently submitted some riscv-related > pull requests; BTW Alistair, should you be listed as a RISC-V > maintainer?) > > Thanks, > > Emilio >
On Tue, Sep 04, 2018 at 13:18:28 -0700, Alistair Francis wrote: > On Fri, Aug 31, 2018 at 3:22 PM, Emilio G. Cota <cota@braap.org> wrote: > > On Fri, Aug 10, 2018 at 13:39:38 -0400, Emilio G. Cota wrote: > >> Changes wrt v1: changed patch 3 as suggested by Richard. Also > >> added his R-b's. > >> > >> You can fetch this series from: > >> https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2 > > > > RISC-V maintainers: any plans of picking this up for 3.1? > > Thanks for CCing me. > > I think Michael must be really busy, I haven't seen any activity for > awhile. I'm going to send a PR with everything that has been reviewed > and applies cleanly. Thanks! Did patch 1 not apply cleanly? I see it's not part of the pullreq you just sent. I'd like the three patches to go in in the original order, since the perf numbers in patch 3's commit log are laid out assuming that is the case. Cheers, Emilio
On Tue, Sep 4, 2018 at 4:39 PM, Emilio G. Cota <cota@braap.org> wrote: > On Tue, Sep 04, 2018 at 13:18:28 -0700, Alistair Francis wrote: >> On Fri, Aug 31, 2018 at 3:22 PM, Emilio G. Cota <cota@braap.org> wrote: >> > On Fri, Aug 10, 2018 at 13:39:38 -0400, Emilio G. Cota wrote: >> >> Changes wrt v1: changed patch 3 as suggested by Richard. Also >> >> added his R-b's. >> >> >> >> You can fetch this series from: >> >> https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2 >> > >> > RISC-V maintainers: any plans of picking this up for 3.1? >> >> Thanks for CCing me. >> >> I think Michael must be really busy, I haven't seen any activity for >> awhile. I'm going to send a PR with everything that has been reviewed >> and applies cleanly. > > Thanks! > > Did patch 1 not apply cleanly? I see it's not part of the pullreq > you just sent. > > I'd like the three patches to go in in the original order, since > the perf numbers in patch 3's commit log are laid out assuming > that is the case. The content of patch 1 was applied in this commit: commit 07ea28b41830f946de3841b0ac61a3413679feb9 Author: Richard Henderson <richard.henderson@linaro.org> Date: Wed May 30 18:06:23 2018 -0700 tcg: Pass tb and index to tcg_gen_exit_tb separately Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> https://github.com/qemu/qemu/commit/07ea28b41830f946de3841b0ac61a3413679feb9 so unfortunately the patch no longer applies. Alistair > > Cheers, > > Emilio
On Tue, Sep 04, 2018 at 16:42:32 -0700, Alistair Francis wrote: > On Tue, Sep 4, 2018 at 4:39 PM, Emilio G. Cota <cota@braap.org> wrote: > > On Tue, Sep 04, 2018 at 13:18:28 -0700, Alistair Francis wrote: > >> On Fri, Aug 31, 2018 at 3:22 PM, Emilio G. Cota <cota@braap.org> wrote: > >> > On Fri, Aug 10, 2018 at 13:39:38 -0400, Emilio G. Cota wrote: > >> >> Changes wrt v1: changed patch 3 as suggested by Richard. Also > >> >> added his R-b's. > >> >> > >> >> You can fetch this series from: > >> >> https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2 > >> > > >> > RISC-V maintainers: any plans of picking this up for 3.1? > >> > >> Thanks for CCing me. > >> > >> I think Michael must be really busy, I haven't seen any activity for > >> awhile. I'm going to send a PR with everything that has been reviewed > >> and applies cleanly. > > > > Thanks! > > > > Did patch 1 not apply cleanly? I see it's not part of the pullreq > > you just sent. > > > > I'd like the three patches to go in in the original order, since > > the perf numbers in patch 3's commit log are laid out assuming > > that is the case. > > The content of patch 1 was applied in this commit: > > commit 07ea28b41830f946de3841b0ac61a3413679feb9 > Author: Richard Henderson <richard.henderson@linaro.org> > Date: Wed May 30 18:06:23 2018 -0700 > > tcg: Pass tb and index to tcg_gen_exit_tb separately > > Do the cast to uintptr_t within the helper, so that the compiler > can type check the pointer argument. We can also do some more > sanity checking of the index argument. > > Reviewed-by: Laurent Vivier <laurent@vivier.eu> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > > https://github.com/qemu/qemu/commit/07ea28b41830f946de3841b0ac61a3413679feb9 > > so unfortunately the patch no longer applies. If I rebase the 3 patches on top of the current master (19b599f7), the 3 patches apply cleanly, including patch 1: --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,7 +135,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targ if (ctx->base.singlestep_enabled) { gen_exception_debug(); } else { - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } } } Did you apply the patches manually or pull from a branch? The latest branch I have on this is: https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2 (although note that that branch doesn't have Richard's R-b tag for patch 3) Thanks, Emilio
On Tue, Sep 4, 2018 at 6:07 PM, Emilio G. Cota <cota@braap.org> wrote: > On Tue, Sep 04, 2018 at 16:42:32 -0700, Alistair Francis wrote: >> On Tue, Sep 4, 2018 at 4:39 PM, Emilio G. Cota <cota@braap.org> wrote: >> > On Tue, Sep 04, 2018 at 13:18:28 -0700, Alistair Francis wrote: >> >> On Fri, Aug 31, 2018 at 3:22 PM, Emilio G. Cota <cota@braap.org> wrote: >> >> > On Fri, Aug 10, 2018 at 13:39:38 -0400, Emilio G. Cota wrote: >> >> >> Changes wrt v1: changed patch 3 as suggested by Richard. Also >> >> >> added his R-b's. >> >> >> >> >> >> You can fetch this series from: >> >> >> https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2 >> >> > >> >> > RISC-V maintainers: any plans of picking this up for 3.1? >> >> >> >> Thanks for CCing me. >> >> >> >> I think Michael must be really busy, I haven't seen any activity for >> >> awhile. I'm going to send a PR with everything that has been reviewed >> >> and applies cleanly. >> > >> > Thanks! >> > >> > Did patch 1 not apply cleanly? I see it's not part of the pullreq >> > you just sent. >> > >> > I'd like the three patches to go in in the original order, since >> > the perf numbers in patch 3's commit log are laid out assuming >> > that is the case. >> >> The content of patch 1 was applied in this commit: >> >> commit 07ea28b41830f946de3841b0ac61a3413679feb9 >> Author: Richard Henderson <richard.henderson@linaro.org> >> Date: Wed May 30 18:06:23 2018 -0700 >> >> tcg: Pass tb and index to tcg_gen_exit_tb separately >> >> Do the cast to uintptr_t within the helper, so that the compiler >> can type check the pointer argument. We can also do some more >> sanity checking of the index argument. >> >> Reviewed-by: Laurent Vivier <laurent@vivier.eu> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> >> https://github.com/qemu/qemu/commit/07ea28b41830f946de3841b0ac61a3413679feb9 >> >> so unfortunately the patch no longer applies. > > If I rebase the 3 patches on top of the current master (19b599f7), > the 3 patches apply cleanly, including patch 1: > > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -135,7 +135,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, targ > if (ctx->base.singlestep_enabled) { > gen_exception_debug(); > } else { > - tcg_gen_exit_tb(NULL, 0); > + tcg_gen_lookup_and_goto_ptr(); > } > } > } > > Did you apply the patches manually or pull from a branch? > The latest branch I have on this is: > https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2 > (although note that that branch doesn't have Richard's > R-b tag for patch 3) I thought I cherry picked them directly from your branch and I saw conflicts. It seems to be working now, maybe I cherry picked the wrong patch. I'll update the PR. Thanks for double checking for me. Alistair > > Thanks, > > Emilio
On Fri, 31 Aug 2018 15:22:49 PDT (-0700), cota@braap.org wrote: > On Fri, Aug 10, 2018 at 13:39:38 -0400, Emilio G. Cota wrote: >> Changes wrt v1: changed patch 3 as suggested by Richard. Also >> added his R-b's. >> >> You can fetch this series from: >> https://github.com/cota/qemu/tree/riscv-lookup_ptr-v2 > > RISC-V maintainers: any plans of picking this up for 3.1? Michael has a better handle on the QEMU patch queue than I do, but I'm starting to free up some time to actually work on this stuff. He'll be in town next week so we'll try to figure out our story for QEMU 3.1. Sorry for being a bit out of it, we've been super busy with some internal projects. > (Cc'ing Alistair since he recently submitted some riscv-related > pull requests; BTW Alistair, should you be listed as a RISC-V > maintainer?) I'm not opposed to Alistair being a maintainer, I'll talk it over with the other guys. It'd be great to have someone active and not at SiFive on QEMU, as when we get busy we tend to all get busy :).