[0/5] Add MSI-X support for cadence EP driver
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Message ID 1532971260-5269-1-git-send-email-adouglas@cadence.com
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  • Add MSI-X support for cadence EP driver
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Alan Douglas July 30, 2018, 5:21 p.m. UTC
Patch series made against Bjorn Helgaas's pci next branch.
It relies on Gustavo Pimentel's patch series adding MSI-X
support in the PCIe EP driver framework, and implements
MSI-X support for the cadence endpoint driver.
 - Use AXI region 0 for interrupt signalling
 - Write MSI and MSI-X with 32bit value rather than 16bit
 - Check for masking before sending MSI or MSI-X
 - Check link is up before sending IRQ
 - Use BAR5 for MSI-X vectors

Alan Douglas (5):
  PCI: cadence: Use AXI region 0 to signal interrupts from EP
  PCI: cadence: Write MSI data with 32bits
  PCI: cadence: Check whether MSI is masked before sending it
  PCI: cadence: Check link is up before sending IRQ from EP
  PCI: cadence: Add MSI-X capability to EP driver

 drivers/pci/controller/pcie-cadence-ep.c |  129 ++++++++++++++++++++++++++++--
 drivers/pci/controller/pcie-cadence.h    |    1 +
 2 files changed, 124 insertions(+), 6 deletions(-)

Comments

Lorenzo Pieralisi Aug. 8, 2018, 4:38 p.m. UTC | #1
Hi Alan,

On Mon, Jul 30, 2018 at 06:21:00PM +0100, Alan Douglas wrote:
> Patch series made against Bjorn Helgaas's pci next branch.

Always rebase patches on a fixed -rc (ie Bjorn and I are using
v4.18-rc1) and mention the dependency rather than rebasing the
series on pci-next please.

> It relies on Gustavo Pimentel's patch series adding MSI-X
> support in the PCIe EP driver framework, and implements
> MSI-X support for the cadence endpoint driver.
>  - Use AXI region 0 for interrupt signalling
>  - Write MSI and MSI-X with 32bit value rather than 16bit
>  - Check for masking before sending MSI or MSI-X
>  - Check link is up before sending IRQ

These first four are fixes or changes required before enabling
the last patch in the series ?

Reworded: does the current driver work without the first 4
patches applied ?

If they are fixes please mark them as such in the commit log.

Thanks,
Lorenzo

>  - Use BAR5 for MSI-X vectors
> 
> Alan Douglas (5):
>   PCI: cadence: Use AXI region 0 to signal interrupts from EP
>   PCI: cadence: Write MSI data with 32bits
>   PCI: cadence: Check whether MSI is masked before sending it
>   PCI: cadence: Check link is up before sending IRQ from EP
>   PCI: cadence: Add MSI-X capability to EP driver
> 
>  drivers/pci/controller/pcie-cadence-ep.c |  129 ++++++++++++++++++++++++++++--
>  drivers/pci/controller/pcie-cadence.h    |    1 +
>  2 files changed, 124 insertions(+), 6 deletions(-)
>
Alan Douglas Aug. 9, 2018, 11:59 a.m. UTC | #2
On  08 August 2018 17:38, Lorenzo Pieralisi wrote:
> On Mon, Jul 30, 2018 at 06:21:00PM +0100, Alan Douglas wrote:
> > Patch series made against Bjorn Helgaas's pci next branch.
> 
> Always rebase patches on a fixed -rc (ie Bjorn and I are using
> v4.18-rc1) and mention the dependency rather than rebasing the
> series on pci-next please.
> 
OK, will do that for v1

> > It relies on Gustavo Pimentel's patch series adding MSI-X
> > support in the PCIe EP driver framework, and implements
> > MSI-X support for the cadence endpoint driver.
> >  - Use AXI region 0 for interrupt signalling
> >  - Write MSI and MSI-X with 32bit value rather than 16bit
> >  - Check for masking before sending MSI or MSI-X
> >  - Check link is up before sending IRQ
> 
> These first four are fixes or changes required before enabling
> the last patch in the series ?
> 
> Reworded: does the current driver work without the first 4
> patches applied ?
> 
> If they are fixes please mark them as such in the commit log.
> 
These are fixes, will mark them as such in the log, and will
split patches such that they can be applied without adding
MSI-X support.

Thanks for your comments,
Alan