[0/6] Tegra PMC pinctrl pad configuration

Message ID	1531226879-11802-1-git-send-email-avienamo@nvidia.com
Headers	show Return-Path: <linux-tegra-owner@vger.kernel.org> TLS: TLSv1, AES128-SHA) id <B5b44ab1d0000>; Tue, 10 Jul 2018 05:48:29 -0700 From: Aapo Vienamo <avienamo@nvidia.com> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Mikko Perttunen <mperttunen@nvidia.com> CC: Aapo Vienamo <avienamo@nvidia.com>, <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH 0/6] Tegra PMC pinctrl pad configuration Date: Tue, 10 Jul 2018 15:47:53 +0300 Message-ID: <1531226879-11802-1-git-send-email-avienamo@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk
Series	Tegra PMC pinctrl pad configuration \| expand [0/6] Tegra PMC pinctrl pad configuration [1/6] soc/tegra: pmc: Fix pad voltage configuration for Tegra186 [2/6] soc/tegra: pmc: Factor out DPD register bit calculation [3/6] soc/tegra: pmc: Implement tegra_io_pad_is_powered() [4/6] soc/tegra: pmc: Use X macro to generate IO pad tables [5/6] dt-bindings: Add Tegra PMC pad configuration bindings [6/6] soc/tegra: pmc: Implement pad configuration via pinctrl

Message ID

1531226879-11802-1-git-send-email-avienamo@nvidia.com

Headers

From: Aapo Vienamo <avienamo@nvidia.com>
To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Mikko Perttunen <mperttunen@nvidia.com>
CC: Aapo Vienamo <avienamo@nvidia.com>, <devicetree@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 0/6] Tegra PMC pinctrl pad configuration
Date: Tue, 10 Jul 2018 15:47:53 +0300
Message-ID: <1531226879-11802-1-git-send-email-avienamo@nvidia.com>
MIME-Version: 1.0
Content-Type: text/plain
Sender: linux-tegra-owner@vger.kernel.org
Precedence: bulk

Series

Tegra PMC pinctrl pad configuration | expand

Message

Aapo Vienamo July 10, 2018, 12:47 p.m. UTC

Hi all,

The Tegra Power Management Controller (PMC) can set pad power states
and voltage configuration. This series implements pinctrl interfaces
for configuring said pad properties.

Aapo Vienamo (6):
  soc/tegra: pmc: Fix pad voltage configuration for Tegra186
  soc/tegra: pmc: Factor out DPD register bit calculation
  soc/tegra: pmc: Implement tegra_io_pad_is_powered()
  soc/tegra: pmc: Use X macro to generate IO pad tables
  dt-bindings: Add Tegra PMC pad configuration bindings
  soc/tegra: pmc: Implement pad configuration via pinctrl

 .../bindings/arm/tegra/nvidia,tegra186-pmc.txt     |  84 ++++
 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  95 ++++
 drivers/soc/tegra/pmc.c                            | 504 ++++++++++++++++-----
 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h |  18 +
 include/soc/tegra/pmc.h                            |   1 +
 5 files changed, 580 insertions(+), 122 deletions(-)
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h