From patchwork Wed May 30 15:06:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 922851 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sGpy/q4S"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40wvD216nBz9s1b for ; Thu, 31 May 2018 01:10:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753373AbeE3PKY (ORCPT ); Wed, 30 May 2018 11:10:24 -0400 Received: from mail-lf0-f68.google.com ([209.85.215.68]:38718 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751684AbeE3PKX (ORCPT ); Wed, 30 May 2018 11:10:23 -0400 Received: by mail-lf0-f68.google.com with SMTP id z142-v6so4849544lff.5; Wed, 30 May 2018 08:10:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=TGZzrBJevyMMvTh5eom2ulrnsLb2810dnjyg7u5ApfY=; b=sGpy/q4S3TqU+fIBrfMdpmF/2Alo+nYoGuquD5CiIusU9rajyTISKEfR4/tPPPwGna 6UXZpo14BTlem3RbWygItd8uzEESYm64GetHG2NLerVd82WzeYfTP+A3OQmHRnn+tMri cx0r1wNSidvtRoqq0UEEf/MjQN+zAuGId4zHSsPTom+9jOtxYwutF9uCIHDBGJKbj42N 2ssTJznT7SOG6L53ThGLTzkzbZGfNi/aSlr0iSLUUEsadjq6UDmXAaZUg34+qcnpNr/k knZRfwMi0aD1V0bCeOlEYnbkFZ82TDeKhIYoCDx5XewJnApZzwnhMTymKTkrC8df3GlX u4Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=TGZzrBJevyMMvTh5eom2ulrnsLb2810dnjyg7u5ApfY=; b=TlHNnCvbl5F8APGiETGgp4xesz9MgzfFlEwSYotnP/6coFAaR3oUe4q+f/5ClPW49x uBe+wuT/Zl3kFd0DnxXbAliGq+UpYHtBBPCz0zkHKwRbVPmj4s3axAi22/MhNejEK/el o8RGCBAMXJAofOZtioQFgj7J5Vzk7H34tkb5e4NysxNb00Xa2mLkuVy1Gkjhx7UyadYg DMqmeBFXfof86xi5plxxb5q07x9p8mboLHkx2wJlB9r3dh70XFUwuDf43jqCNjUnlXRZ jr/DMVc9ZeIj9JlgE0wjlkpM9goJRukQhhCWvk2WPGGUCQy3D3wczkPPXsBvSPgiaWbC Q2Vw== X-Gm-Message-State: ALKqPweTFk58FGgSh/VWxmnkB1y0aATbaAOt1ZYliasYUHu0uV7NhfsI Z3n/wzqo7q13M2TyHx+Yjmg= X-Google-Smtp-Source: ADUXVKLS90zFr0yWobMJfU47PbO058JzuBWd94i2MjzDWpJ1r6ngCCn1CvGcJ70b+dQ9Qo4Kfw1zZA== X-Received: by 2002:a19:ca0b:: with SMTP id a11-v6mr1905670lfg.69.1527693021592; Wed, 30 May 2018 08:10:21 -0700 (PDT) Received: from localhost.localdomain (109-252-91-41.nat.spd-mgts.ru. [109.252.91.41]) by smtp.gmail.com with ESMTPSA id v3-v6sm6982134ljv.61.2018.05.30.08.10.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 08:10:20 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Peter De Schrijver , Jonathan Hunter , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 0/4] Tegra20 External Memory Controller driver Date: Wed, 30 May 2018 18:06:42 +0300 Message-Id: <20180530150646.19030-1-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Hello, Couple years ago the Tegra20 EMC driver was removed from the kernel due to incompatible changes in the Tegra's clock driver. This patchset introduces a modernized EMC driver. Currently the sole purpose of the driver is to initialize DRAM frequency to maximum rate during of the kernels boot-up. Later we may consider implementing dynamic memory frequency scaling, utilizing functionality provided by this driver. Dmitry Osipenko (4): dt: bindings: tegra20-emc: Document interrupt property ARM: dts: tegra20: Add interrupt to External Memory Controller clk: tegra20: Turn EMC clock gate into divider memory: tegra: Introduce Tegra20 EMC driver .../bindings/arm/tegra/nvidia,tegra20-emc.txt | 2 + arch/arm/boot/dts/tegra20.dtsi | 1 + drivers/clk/tegra/clk-tegra20.c | 39 +- drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/tegra20-emc.c | 573 ++++++++++++++++++ 6 files changed, 616 insertions(+), 10 deletions(-) create mode 100644 drivers/memory/tegra/tegra20-emc.c