| Message ID | 1526375616-16904-1-git-send-email-ilialin@codeaurora.org |
|---|---|
| Headers | show |
| Series | CPU scaling support for msm8996 | expand |
On Tuesday, May 15, 2018 11:19:12 AM CEST Viresh Kumar wrote: > On 15-05-18, 12:13, Ilia Lin wrote: > > In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, > > the CPU ferequencies subset and voltage value of each OPP varies > > based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables > > defines the voltage and frequency value based on the msm-id in SMEM > > and speedbin blown in the efuse combination. > > The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC > > to provide the OPP framework with required information. > > This is used to determine the voltage and frequency value for each OPP of > > operating-points-v2 table when it is parsed by the OPP framework. > > > > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > > --- > > drivers/cpufreq/Kconfig.arm | 11 +++ > > drivers/cpufreq/Makefile | 1 + > > drivers/cpufreq/cpufreq-dt-platdev.c | 3 + > > drivers/cpufreq/qcom-cpufreq-kryo.c | 150 +++++++++++++++++++++++++++++++++++ > > 4 files changed, 165 insertions(+) > > create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c > > Acked-by: Viresh Kumar <viresh.kumar@linaro.org> OK, but I'm assuming that this will go in via arm-soc. Thanks, Rafael -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote: > [v7] > * Addressed comments from Viresh about resourses deallocation > and DT compatible Hi Ilia, Thanks for working on this series. Here a few comments regarding the series as a whole. - The series could use a better cover letter describing how the various patches are grouped. e.g. 1-7 are clock related and probably will get merged through the clk maintainers tree. The regulator bits might get merged through the regulator maintainer tree and so forth. If there are any dependencies, please outline those as well so maintainers can decide how best to merge this. - Please describe what features this series adds - just frequency scaling or more. Please describe in more detail what the dependency on the SAW regulator changes is. - Please get rid of the GPL boiler plate since you already have the SPDX tags. See comments on patch 1 for what I'm referring to. - You also mention that ACD is not implemented in the earlier patches and then there is a patch that seems to add ACD related features (7/14). A few other comments follow across the individual patches. Regards, Amit > [v6] > * Addressed comments from Viresh about: > ** Comments style > ** Kconfig bool instead of tristate > ** DT and documentation style > ** Resourses deallocation on an error > ** Typos > > [v5] > * Rebased > * Addressed comments from Bjorn about SPDX style, > functions and parameters naming > * Addressed comments from Viresh DT properties and style, comments style, > resourses deallocation, documentation placement > * Addressed comments from Sricharan about unnessesary include > * Addressed comments from Nicolas > * Addressed comments from Rob about the commit messages and acks > * Addressed comments from Mark > > [v4] > * Adressed all comments from Stephen > * Added CPU regulator support > * Added qcom-cpufreq-kryo driver > > [v3] > * Rebased on top of the latest PLL driver changes > * Addressed comment from Rob Herring for bindings > > [v2] > * Addressed comments from Rob Herring for bindings > * Addressed comments from Mark Rutland for memory barrier > * Addressed comments from Julien Thierry for clock reenabling condition > * Tuned the HW configuration for clock frequencies below 600MHz > > Clocks: > This series adds support for the CPU clocks on msm8996 devices. > The driver uses the existing PLL drivers and is required to control > the CPU frequency scaling on the MSM8996. > > Regulators: > Added SAW regulator support to the SPMI regulator driver. The SAW regulators > will be controlled through special CPU registers instead of direct > SPMI accesses. > > Cpufreq: > The qcom-cpufreq-kryo driver is aimed to support different SOC versions. > The driver reads eFuse information and chooses the required OPP subset > by passing the OPP supported-hw parameter. > > A previous post of RFC can be found here: > https://patchwork.kernel.org/patch/10398455/ > > Ilia Lin (11): > soc: qcom: Separate kryo l2 accessors from PMU driver > clk: qcom: Add CPU clock driver for msm8996 > clk: qcom: Add DT bindings for CPU clock driver for msm8996 > clk: qcom: Add ACD path to CPU clock driver for msm8996 > dt: qcom: Add opp and thermal to the msm8996 > regulator: qcom_spmi: Add support for SAW > dt-bindings: qcom_spmi: Add support for SAW documentation > dt: qcom: Add SAW regulator for 8x96 CPUs > cpufreq: Add Kryo CPU scaling driver > dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu > dt: qcom: Add qcom-cpufreq-kryo driver configuration > > Rajendra Nayak (3): > clk: qcom: Make clk_alpha_pll_configure available to modules > clk: qcom: cpu-8996: Add support to switch to alternate PLL > clk: qcom: cpu-8996: Add support to switch below 600Mhz > > .../devicetree/bindings/clock/qcom,kryocc.txt | 17 + > .../devicetree/bindings/opp/kryo-cpufreq.txt | 680 +++++++++++++++++++++ > .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++ > arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 651 +++++++++++++++++++- > drivers/clk/clk-fixed-factor.c | 2 +- > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clk-alpha-pll.c | 1 + > drivers/clk/qcom/clk-alpha-pll.h | 6 + > drivers/clk/qcom/clk-cpu-8996.c | 519 ++++++++++++++++ > drivers/cpufreq/Kconfig.arm | 11 + > drivers/cpufreq/Makefile | 1 + > drivers/cpufreq/cpufreq-dt-platdev.c | 3 + > drivers/cpufreq/qcom-cpufreq-kryo.c | 150 +++++ > drivers/perf/Kconfig | 1 + > drivers/perf/qcom_l2_pmu.c | 90 +-- > drivers/regulator/qcom_spmi-regulator.c | 133 +++- > drivers/soc/qcom/Kconfig | 3 + > drivers/soc/qcom/Makefile | 1 + > drivers/soc/qcom/kryo-l2-accessors.c | 65 ++ > include/soc/qcom/kryo-l2-accessors.h | 21 + > 22 files changed, 2332 insertions(+), 80 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,kryocc.txt > create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt > create mode 100644 drivers/clk/qcom/clk-cpu-8996.c > create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c > create mode 100644 drivers/soc/qcom/kryo-l2-accessors.c > create mode 100644 include/soc/qcom/kryo-l2-accessors.h > > -- > 1.9.1 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote: > The driver provides kernel level API for other drivers > to access the MSM8996 L2 cache registers. > Separating the L2 access code from the PMU driver and > making it public to allow other drivers use it. > The accesses must be separated with a single spinlock, > maintained in this driver. > > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > --- > drivers/perf/Kconfig | 1 + > drivers/perf/qcom_l2_pmu.c | 90 ++++++++++-------------------------- > drivers/soc/qcom/Kconfig | 3 ++ > drivers/soc/qcom/Makefile | 1 + > drivers/soc/qcom/kryo-l2-accessors.c | 65 ++++++++++++++++++++++++++ > include/soc/qcom/kryo-l2-accessors.h | 21 +++++++++ > 6 files changed, 115 insertions(+), 66 deletions(-) > create mode 100644 drivers/soc/qcom/kryo-l2-accessors.c > create mode 100644 include/soc/qcom/kryo-l2-accessors.h > > diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig > index 28bb5a0..561252a 100644 > --- a/drivers/perf/Kconfig > +++ b/drivers/perf/Kconfig > @@ -69,6 +69,7 @@ config HISI_PMU > config QCOM_L2_PMU > bool "Qualcomm Technologies L2-cache PMU" > depends on ARCH_QCOM && ARM64 && ACPI > + select QCOM_KRYO_L2_ACCESSORS > help > Provides support for the L2 cache performance monitor unit (PMU) > in Qualcomm Technologies processors. > diff --git a/drivers/perf/qcom_l2_pmu.c b/drivers/perf/qcom_l2_pmu.c > index 842135c..cc31f51 100644 > --- a/drivers/perf/qcom_l2_pmu.c > +++ b/drivers/perf/qcom_l2_pmu.c > @@ -31,6 +31,7 @@ > #include <asm/barrier.h> > #include <asm/local64.h> > #include <asm/sysreg.h> > +#include <soc/qcom/kryo-l2-accessors.h> > > #define MAX_L2_CTRS 9 > > @@ -87,8 +88,6 @@ > #define L2_COUNTER_RELOAD BIT_ULL(31) > #define L2_CYCLE_COUNTER_RELOAD BIT_ULL(63) > > -#define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6) > -#define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7) > > #define reg_idx(reg, i) (((i) * IA_L2_REG_OFFSET) + reg##_BASE) > > @@ -107,48 +106,7 @@ > #define L2_EVENT_STREX 0x421 > #define L2_EVENT_CLREX 0x422 > > -static DEFINE_RAW_SPINLOCK(l2_access_lock); > > -/** > - * set_l2_indirect_reg: write value to an L2 register > - * @reg: Address of L2 register. > - * @value: Value to be written to register. > - * > - * Use architecturally required barriers for ordering between system register > - * accesses > - */ > -static void set_l2_indirect_reg(u64 reg, u64 val) > -{ > - unsigned long flags; > - > - raw_spin_lock_irqsave(&l2_access_lock, flags); > - write_sysreg_s(reg, L2CPUSRSELR_EL1); > - isb(); > - write_sysreg_s(val, L2CPUSRDR_EL1); > - isb(); > - raw_spin_unlock_irqrestore(&l2_access_lock, flags); > -} > - > -/** > - * get_l2_indirect_reg: read an L2 register value > - * @reg: Address of L2 register. > - * > - * Use architecturally required barriers for ordering between system register > - * accesses > - */ > -static u64 get_l2_indirect_reg(u64 reg) > -{ > - u64 val; > - unsigned long flags; > - > - raw_spin_lock_irqsave(&l2_access_lock, flags); > - write_sysreg_s(reg, L2CPUSRSELR_EL1); > - isb(); > - val = read_sysreg_s(L2CPUSRDR_EL1); > - raw_spin_unlock_irqrestore(&l2_access_lock, flags); > - > - return val; > -} > > struct cluster_pmu; > > @@ -219,28 +177,28 @@ static inline struct cluster_pmu *get_cluster_pmu( > static void cluster_pmu_reset(void) > { > /* Reset all counters */ > - set_l2_indirect_reg(L2PMCR, L2PMCR_RESET_ALL); > - set_l2_indirect_reg(L2PMCNTENCLR, l2_counter_present_mask); > - set_l2_indirect_reg(L2PMINTENCLR, l2_counter_present_mask); > - set_l2_indirect_reg(L2PMOVSCLR, l2_counter_present_mask); > + kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_RESET_ALL); > + kryo_l2_set_indirect_reg(L2PMCNTENCLR, l2_counter_present_mask); > + kryo_l2_set_indirect_reg(L2PMINTENCLR, l2_counter_present_mask); > + kryo_l2_set_indirect_reg(L2PMOVSCLR, l2_counter_present_mask); > } > > static inline void cluster_pmu_enable(void) > { > - set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_ENABLE); > + kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_COUNTERS_ENABLE); > } > > static inline void cluster_pmu_disable(void) > { > - set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_DISABLE); > + kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_COUNTERS_DISABLE); > } > > static inline void cluster_pmu_counter_set_value(u32 idx, u64 value) > { > if (idx == l2_cycle_ctr_idx) > - set_l2_indirect_reg(L2PMCCNTR, value); > + kryo_l2_set_indirect_reg(L2PMCCNTR, value); > else > - set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value); > + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value); > } > > static inline u64 cluster_pmu_counter_get_value(u32 idx) > @@ -248,46 +206,46 @@ static inline u64 cluster_pmu_counter_get_value(u32 idx) > u64 value; > > if (idx == l2_cycle_ctr_idx) > - value = get_l2_indirect_reg(L2PMCCNTR); > + value = kryo_l2_get_indirect_reg(L2PMCCNTR); > else > - value = get_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx)); > + value = kryo_l2_get_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx)); > > return value; > } > > static inline void cluster_pmu_counter_enable(u32 idx) > { > - set_l2_indirect_reg(L2PMCNTENSET, idx_to_reg_bit(idx)); > + kryo_l2_set_indirect_reg(L2PMCNTENSET, idx_to_reg_bit(idx)); > } > > static inline void cluster_pmu_counter_disable(u32 idx) > { > - set_l2_indirect_reg(L2PMCNTENCLR, idx_to_reg_bit(idx)); > + kryo_l2_set_indirect_reg(L2PMCNTENCLR, idx_to_reg_bit(idx)); > } > > static inline void cluster_pmu_counter_enable_interrupt(u32 idx) > { > - set_l2_indirect_reg(L2PMINTENSET, idx_to_reg_bit(idx)); > + kryo_l2_set_indirect_reg(L2PMINTENSET, idx_to_reg_bit(idx)); > } > > static inline void cluster_pmu_counter_disable_interrupt(u32 idx) > { > - set_l2_indirect_reg(L2PMINTENCLR, idx_to_reg_bit(idx)); > + kryo_l2_set_indirect_reg(L2PMINTENCLR, idx_to_reg_bit(idx)); > } > > static inline void cluster_pmu_set_evccntcr(u32 val) > { > - set_l2_indirect_reg(L2PMCCNTCR, val); > + kryo_l2_set_indirect_reg(L2PMCCNTCR, val); > } > > static inline void cluster_pmu_set_evcntcr(u32 ctr, u32 val) > { > - set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val); > + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val); > } > > static inline void cluster_pmu_set_evtyper(u32 ctr, u32 val) > { > - set_l2_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val); > + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val); > } > > static void cluster_pmu_set_resr(struct cluster_pmu *cluster, > @@ -303,11 +261,11 @@ static void cluster_pmu_set_resr(struct cluster_pmu *cluster, > > spin_lock_irqsave(&cluster->pmu_lock, flags); > > - resr_val = get_l2_indirect_reg(L2PMRESR); > + resr_val = kryo_l2_get_indirect_reg(L2PMRESR); > resr_val &= ~(L2PMRESR_GROUP_MASK << shift); > resr_val |= field; > resr_val |= L2PMRESR_EN; > - set_l2_indirect_reg(L2PMRESR, resr_val); > + kryo_l2_set_indirect_reg(L2PMRESR, resr_val); > > spin_unlock_irqrestore(&cluster->pmu_lock, flags); > } > @@ -323,14 +281,14 @@ static inline void cluster_pmu_set_evfilter_sys_mode(u32 ctr) > L2PMXEVFILTER_ORGFILTER_IDINDEP | > L2PMXEVFILTER_ORGFILTER_ALL; > > - set_l2_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val); > + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val); > } > > static inline u32 cluster_pmu_getreset_ovsr(void) > { > - u32 result = get_l2_indirect_reg(L2PMOVSSET); > + u32 result = kryo_l2_get_indirect_reg(L2PMOVSSET); > > - set_l2_indirect_reg(L2PMOVSCLR, result); > + kryo_l2_set_indirect_reg(L2PMOVSCLR, result); > return result; > } > > @@ -783,7 +741,7 @@ static int get_num_counters(void) > { > int val; > > - val = get_l2_indirect_reg(L2PMCR); > + val = kryo_l2_get_indirect_reg(L2PMCR); > > /* > * Read number of counters from L2PMCR and add 1 > diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig > index 7093fe7..0567dff 100644 > --- a/drivers/soc/qcom/Kconfig > +++ b/drivers/soc/qcom/Kconfig > @@ -39,6 +39,9 @@ config QCOM_GSBI > functions for connecting the underlying serial UART, SPI, and I2C > devices to the output pins. > > +config QCOM_KRYO_L2_ACCESSORS > + bool > + > config QCOM_MDT_LOADER > tristate > select QCOM_SCM > diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile > index cbf414c..e4d3f5a 100644 > --- a/drivers/soc/qcom/Makefile > +++ b/drivers/soc/qcom/Makefile > @@ -14,3 +14,4 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o > obj-$(CONFIG_QCOM_SMP2P) += smp2p.o > obj-$(CONFIG_QCOM_SMSM) += smsm.o > obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o > +obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o > diff --git a/drivers/soc/qcom/kryo-l2-accessors.c b/drivers/soc/qcom/kryo-l2-accessors.c > new file mode 100644 > index 0000000..d35a860 > --- /dev/null > +++ b/drivers/soc/qcom/kryo-l2-accessors.c > @@ -0,0 +1,65 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2014-2015, 2018, The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + Get rid of the GPL boilerplate i.e. everything after the Copyright line. You only need the SPDX line at the top. > +#include <linux/spinlock.h> > +#include <asm/sysreg.h> > +#include <soc/qcom/kryo-l2-accessors.h> > + > +#define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6) > +#define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7) > + > +static DEFINE_RAW_SPINLOCK(l2_access_lock); > + > +/** > + * kryo_l2_set_indirect_reg() - write value to an L2 register > + * @reg: Address of L2 register. > + * @value: Value to be written to register. > + * > + * Use architecturally required barriers for ordering between system register > + * accesses, and system registers with respect to device memory > + */ > +void kryo_l2_set_indirect_reg(u64 reg, u64 val) > +{ > + unsigned long flags; > + > + raw_spin_lock_irqsave(&l2_access_lock, flags); > + write_sysreg_s(reg, L2CPUSRSELR_EL1); > + isb(); > + write_sysreg_s(val, L2CPUSRDR_EL1); > + isb(); > + raw_spin_unlock_irqrestore(&l2_access_lock, flags); > +} > +EXPORT_SYMBOL(kryo_l2_set_indirect_reg); > + > +/** > + * kryo_l2_get_indirect_reg() - read an L2 register value > + * @reg: Address of L2 register. > + * > + * Use architecturally required barriers for ordering between system register > + * accesses, and system registers with respect to device memory > + */ > +u64 kryo_l2_get_indirect_reg(u64 reg) > +{ > + u64 val; > + unsigned long flags; > + > + raw_spin_lock_irqsave(&l2_access_lock, flags); > + write_sysreg_s(reg, L2CPUSRSELR_EL1); > + isb(); > + val = read_sysreg_s(L2CPUSRDR_EL1); > + raw_spin_unlock_irqrestore(&l2_access_lock, flags); > + > + return val; > +} > +EXPORT_SYMBOL(kryo_l2_get_indirect_reg); > diff --git a/include/soc/qcom/kryo-l2-accessors.h b/include/soc/qcom/kryo-l2-accessors.h > new file mode 100644 > index 0000000..0840e87 > --- /dev/null > +++ b/include/soc/qcom/kryo-l2-accessors.h > @@ -0,0 +1,21 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ Get rid of the GPL boilerplate i.e. everything after the Copyright line. You only need the SPDX line at the top. > +#ifndef __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H > +#define __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H > + > +void kryo_l2_set_indirect_reg(u64 reg, u64 val); > +u64 kryo_l2_get_indirect_reg(u64 reg); > + > +#endif > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
2018-05-15 12:13 GMT+03:00 Ilia Lin <ilialin@codeaurora.org>: No commit message? Perhaps something listing the different hw types? > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 311 +++++++++++++++++++++++++++- > 2 files changed, 310 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts > index 230e9c8..da23bda 100644 > --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts > +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts > @@ -17,5 +17,5 @@ > > / { > model = "Qualcomm Technologies, Inc. DB820c"; > - compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc"; > + compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; > }; > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index d7adef9..1dedfb8 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -174,218 +174,520 @@ > }; > > cluster0_opp: opp_table0 { > - compatible = "operating-points-v2"; > + compatible = "operating-points-v2-kryo-cpu", > + "operating-points-v2"; > + nvmem-cells = <&speedbin_efuse>; > opp-shared; > > opp-307200000 { > opp-hz = /bits/ 64 <307200000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-384000000 { > + opp-hz = /bits/ 64 <384000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-422400000 { > opp-hz = /bits/ 64 <422400000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-460800000 { > + opp-hz = /bits/ 64 <460800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-480000000 { > opp-hz = /bits/ 64 <480000000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-537600000 { > + opp-hz = /bits/ 64 <537600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-556800000 { > opp-hz = /bits/ 64 <556800000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-614400000 { > + opp-hz = /bits/ 64 <614400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-652800000 { > opp-hz = /bits/ 64 <652800000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-691200000 { > + opp-hz = /bits/ 64 <691200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-729600000 { > opp-hz = /bits/ 64 <729600000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-768000000 { > + opp-hz = /bits/ 64 <768000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-844800000 { > opp-hz = /bits/ 64 <844800000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-902400000 { > + opp-hz = /bits/ 64 <902400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-960000000 { > opp-hz = /bits/ 64 <960000000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-979200000 { > + opp-hz = /bits/ 64 <979200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1036800000 { > opp-hz = /bits/ 64 <1036800000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1056000000 { > + opp-hz = /bits/ 64 <1056000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1113600000 { > opp-hz = /bits/ 64 <1113600000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1132800000 { > + opp-hz = /bits/ 64 <1132800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1190400000 { > opp-hz = /bits/ 64 <1190400000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1209600000 { > + opp-hz = /bits/ 64 <1209600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1228800000 { > opp-hz = /bits/ 64 <1228800000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1286400000 { > + opp-hz = /bits/ 64 <1286400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1324800000 { > opp-hz = /bits/ 64 <1324800000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x5>; > + clock-latency-ns = <200000>; > + }; > + opp-1363200000 { > + opp-hz = /bits/ 64 <1363200000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x72>; > clock-latency-ns = <200000>; > }; > opp-1401600000 { > opp-hz = /bits/ 64 <1401600000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x5>; > + clock-latency-ns = <200000>; > + }; > + opp-1440000000 { > + opp-hz = /bits/ 64 <1440000000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1478400000 { > opp-hz = /bits/ 64 <1478400000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + opp-1497600000 { > + opp-hz = /bits/ 64 <1497600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x4>; > + clock-latency-ns = <200000>; > + }; > + opp-1516800000 { > + opp-hz = /bits/ 64 <1516800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1593600000 { > opp-hz = /bits/ 64 <1593600000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x71>; > + clock-latency-ns = <200000>; > + }; > + opp-1996800000 { > + opp-hz = /bits/ 64 <1996800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x20>; > + clock-latency-ns = <200000>; > + }; > + opp-2188800000 { > + opp-hz = /bits/ 64 <2188800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x10>; > clock-latency-ns = <200000>; > }; > }; > > cluster1_opp: opp_table1 { > - compatible = "operating-points-v2"; > + compatible = "operating-points-v2-kryo-cpu"; > + nvmem-cells = <&speedbin_efuse>; > opp-shared; > > opp-307200000 { > opp-hz = /bits/ 64 <307200000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x77>; > + clock-latency-ns = <200000>; > + }; > + opp-384000000 { > + opp-hz = /bits/ 64 <384000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-403200000 { > opp-hz = /bits/ 64 <403200000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-460800000 { > + opp-hz = /bits/ 64 <460800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-480000000 { > opp-hz = /bits/ 64 <480000000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-537600000 { > + opp-hz = /bits/ 64 <537600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-556800000 { > opp-hz = /bits/ 64 <556800000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-614400000 { > + opp-hz = /bits/ 64 <614400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-652800000 { > opp-hz = /bits/ 64 <652800000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-691200000 { > + opp-hz = /bits/ 64 <691200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-729600000 { > opp-hz = /bits/ 64 <729600000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-748800000 { > + opp-hz = /bits/ 64 <748800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-806400000 { > opp-hz = /bits/ 64 <806400000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-825600000 { > + opp-hz = /bits/ 64 <825600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-883200000 { > opp-hz = /bits/ 64 <883200000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-902400000 { > + opp-hz = /bits/ 64 <902400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-940800000 { > opp-hz = /bits/ 64 <940800000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-979200000 { > + opp-hz = /bits/ 64 <979200000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1036800000 { > opp-hz = /bits/ 64 <1036800000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1056000000 { > + opp-hz = /bits/ 64 <1056000000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1113600000 { > opp-hz = /bits/ 64 <1113600000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1132800000 { > + opp-hz = /bits/ 64 <1132800000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1190400000 { > opp-hz = /bits/ 64 <1190400000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1209600000 { > + opp-hz = /bits/ 64 <1209600000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1248000000 { > opp-hz = /bits/ 64 <1248000000>; > opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1286400000 { > + opp-hz = /bits/ 64 <1286400000>; > + opp-microvolt = <905000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1324800000 { > opp-hz = /bits/ 64 <1324800000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1363200000 { > + opp-hz = /bits/ 64 <1363200000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1401600000 { > opp-hz = /bits/ 64 <1401600000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1440000000 { > + opp-hz = /bits/ 64 <1440000000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1478400000 { > opp-hz = /bits/ 64 <1478400000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1516800000 { > + opp-hz = /bits/ 64 <1516800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1555200000 { > opp-hz = /bits/ 64 <1555200000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1593600000 { > + opp-hz = /bits/ 64 <1593600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1632000000 { > opp-hz = /bits/ 64 <1632000000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1670400000 { > + opp-hz = /bits/ 64 <1670400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1708800000 { > opp-hz = /bits/ 64 <1708800000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1747200000 { > + opp-hz = /bits/ 64 <1747200000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x70>; > clock-latency-ns = <200000>; > }; > opp-1785600000 { > opp-hz = /bits/ 64 <1785600000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x7>; > + clock-latency-ns = <200000>; > + }; > + opp-1804800000 { > + opp-hz = /bits/ 64 <1804800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x6>; > clock-latency-ns = <200000>; > }; > opp-1824000000 { > opp-hz = /bits/ 64 <1824000000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x71>; > + clock-latency-ns = <200000>; > + }; > + opp-1900800000 { > + opp-hz = /bits/ 64 <1900800000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x74>; > clock-latency-ns = <200000>; > }; > opp-1920000000 { > opp-hz = /bits/ 64 <1920000000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + opp-1977600000 { > + opp-hz = /bits/ 64 <1977600000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x30>; > clock-latency-ns = <200000>; > }; > opp-1996800000 { > opp-hz = /bits/ 64 <1996800000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x1>; > + clock-latency-ns = <200000>; > + }; > + opp-2054400000 { > + opp-hz = /bits/ 64 <2054400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x30>; > clock-latency-ns = <200000>; > }; > opp-2073600000 { > opp-hz = /bits/ 64 <2073600000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x1>; > clock-latency-ns = <200000>; > }; > opp-2150400000 { > opp-hz = /bits/ 64 <2150400000>; > opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x31>; > + clock-latency-ns = <200000>; > + }; > + opp-2246400000 { > + opp-hz = /bits/ 64 <2246400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x10>; > + clock-latency-ns = <200000>; > + }; > + opp-2342400000 { > + opp-hz = /bits/ 64 <2342400000>; > + opp-microvolt = <1140000 905000 1140000>; > + opp-supported-hw = <0x10>; > clock-latency-ns = <200000>; > }; > }; > @@ -992,6 +1294,11 @@ > reg = <0x24f 0x1>; > bits = <1 4>; > }; > + > + speedbin_efuse: speedbin@133 { > + reg = <0x133 0x1>; > + bits = <5 3>; > + }; > }; > > phy@34000 { > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote: > In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors, > the CPU ferequencies subset and voltage value of each OPP varies s/ferequencies/frequency > based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables > defines the voltage and frequency value based on the msm-id in SMEM > and speedbin blown in the efuse combination. > The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC > to provide the OPP framework with required information. > This is used to determine the voltage and frequency value for each OPP of > operating-points-v2 table when it is parsed by the OPP framework. > > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > --- > drivers/cpufreq/Kconfig.arm | 11 +++ > drivers/cpufreq/Makefile | 1 + > drivers/cpufreq/cpufreq-dt-platdev.c | 3 + > drivers/cpufreq/qcom-cpufreq-kryo.c | 150 +++++++++++++++++++++++++++++++++++ > 4 files changed, 165 insertions(+) > create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c > > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm > index de55c7d..5c16f05 100644 > --- a/drivers/cpufreq/Kconfig.arm > +++ b/drivers/cpufreq/Kconfig.arm > @@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ > depends on ARCH_OMAP2PLUS > default ARCH_OMAP2PLUS > > +config ARM_QCOM_CPUFREQ_KRYO > + bool "Qualcomm Technologies, Inc. Kryo based CPUFreq" "Qualcomm Kryo CPUFreq support" should be enough. Kconfig isn't the place for Trademark compliance :-) > + depends on QCOM_QFPROM > + depends on QCOM_SMEM > + select PM_OPP > + help > + This adds the CPUFreq driver for > + Qualcomm Technologies, Inc. Kryo SoC based boards. > + > + If in doubt, say N. > + > config ARM_S3C_CPUFREQ > bool > help > diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile > index 8d24ade..fb4a2ec 100644 > --- a/drivers/cpufreq/Makefile > +++ b/drivers/cpufreq/Makefile > @@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o > obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o > obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o > obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o > +obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o > obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o > obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o > obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c > index 3b585e4..77d6ab8 100644 > --- a/drivers/cpufreq/cpufreq-dt-platdev.c > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c > @@ -118,6 +118,9 @@ > > { .compatible = "nvidia,tegra124", }, > > + { .compatible = "qcom,apq8096", }, > + { .compatible = "qcom,msm8996", }, > + > { .compatible = "st,stih407", }, > { .compatible = "st,stih410", }, > > diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c b/drivers/cpufreq/qcom-cpufreq-kryo.c > new file mode 100644 > index 0000000..10d7236 > --- /dev/null > +++ b/drivers/cpufreq/qcom-cpufreq-kryo.c > @@ -0,0 +1,150 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* Stray space here. > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/cpu.h> > +#include <linux/err.h> > +#include <linux/init.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/nvmem-consumer.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/pm_opp.h> > +#include <linux/slab.h> > +#include <linux/soc/qcom/smem.h> > + > +#define MSM_ID_SMEM 137 > +#define SILVER_LEAD 0 > +#define GOLD_LEAD 2 > + > +enum _msm_id { > + MSM8996V3 = 0xF6ul, > + APQ8096V3 = 0x123ul, > + MSM8996SG = 0x131ul, > + APQ8096SG = 0x138ul, > +}; > + > +enum _msm8996_version { > + MSM8996_V3, > + MSM8996_SG, > + NUM_OF_MSM8996_VERSIONS, > +}; > + > +static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void) > +{ > + size_t len; > + u32 *msm_id; > + enum _msm8996_version version; > + > + msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len); > + /* The first 4 bytes are format, next to them is the actual msm-id */ > + msm_id++; > + > + switch ((enum _msm_id)*msm_id) { > + case MSM8996V3: > + case APQ8096V3: > + version = MSM8996_V3; > + break; > + case MSM8996SG: > + case APQ8096SG: > + version = MSM8996_SG; > + break; > + default: > + version = NUM_OF_MSM8996_VERSIONS; > + } > + > + return version; > +} > + > +static int __init qcom_cpufreq_kryo_driver_init(void) > +{ > + size_t len; > + int ret; > + u32 versions; > + enum _msm8996_version msm8996_version; > + u8 *speedbin; > + struct device *cpu_dev; > + struct device_node *np; > + struct nvmem_cell *speedbin_nvmem; > + struct opp_table *opp_temp = NULL; > + > + cpu_dev = get_cpu_device(SILVER_LEAD); > + if (IS_ERR_OR_NULL(cpu_dev)) > + return PTR_ERR(cpu_dev); > + > + msm8996_version = qcom_cpufreq_kryo_get_msm_id(); > + if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { > + dev_err(cpu_dev, "Not Snapdragon 820/821!"); > + return -ENODEV; > + } Use tab instead of spaces. > + > + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); > + if (IS_ERR_OR_NULL(np)) > + return PTR_ERR(np); > + > + if (!of_device_is_compatible(np, "operating-points-v2-kryo-cpu")) { > + ret = -ENOENT; > + goto free_np; > + } > + > + speedbin_nvmem = of_nvmem_cell_get(np, NULL); > + if (IS_ERR(speedbin_nvmem)) { > + ret = PTR_ERR(speedbin_nvmem); > + dev_err(cpu_dev, "Could not get nvmem cell: %d\n", ret); > + goto free_np; > + } > + > + speedbin = nvmem_cell_read(speedbin_nvmem, &len); > + > + switch (msm8996_version) { > + case MSM8996_V3: > + versions = 1 << (unsigned int)(*speedbin); > + break; > + case MSM8996_SG: > + versions = 1 << ((unsigned int)(*speedbin) + 4); > + break; > + default: > + BUG(); > + break; > + } > + > + ret = PTR_ERR_OR_ZERO(opp_temp = > + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > + if (0 > ret) Any particular reason to prefer this over (ret < 0) that is generally used? I've seen it used to avoid the == vs. = typos, but not for other comparisons. Suggest sticking to what is commonly used i.e. ret < 0. > + goto free_opp; > + > + cpu_dev = get_cpu_device(GOLD_LEAD); Error check cpu_dev here? > + ret = PTR_ERR_OR_ZERO(opp_temp = > + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > + if (0 > ret) > + goto free_opp; > + > + > + ret = PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq-dt", > + -1, NULL, 0)); > + > + if (0 == ret) > + return 0; > + > +free_opp: > + dev_pm_opp_put_supported_hw(opp_temp); This is not needed because dev_pm_opp_set_supported_hw will free memory in case of failure. This call in only needed in case of a successful get. > + > +free_np: > + of_node_put(np); > + return ret; Suggest something like this instead: . . opp_temp = dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); if (IS_ERR(opp_temp)) { dev_err(cpu_dev, "Failed to set supported hardware\n"); ret = PTR_ERR(opp_temp); goto free_np; } cpu_dev = get_cpu_device(GOLD_LEAD); opp_temp = dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); if (IS_ERR(opp_temp)) { dev_err(cpu_dev, "Failed to set supported hardware\n"); ret = PTR_ERR(opp_temp); goto free_np; } ret = platform_device_register_simple("cpufreq-dt", -1, NULL, 0)); if (!IS_ERR_OR_NULL(ret)) goto out; free_np: of_node_put(np); out: return ret; > +} > +late_initcall(qcom_cpufreq_kryo_driver_init); > + > +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver"); > +MODULE_LICENSE("GPL v2"); > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote: > Each of the CPU clusters (Power and Perf) on msm8996 are > clocked via 2 PLLs, a primary and alternate. There are also > 2 Mux'es, a primary and secondary all connected together > as shown below > > +-------+ > XO | | > +------------------>0 | > | | > PLL/2 | SMUX +----+ > +------->1 | | > | | | | > | +-------+ | +-------+ > | +---->0 | > | | | > +---------------+ | +----------->1 | CPU clk > |Primary PLL +----+ PLL_EARLY | | +------> > | +------+-----------+ +------>2 PMUX | > +---------------+ | | | | > | +------+ | +-->3 | > +--^+ ACD +-----+ | +-------+ > +---------------+ +------+ | > |Alt PLL | | > | +---------------------------+ > +---------------+ PLL_EARLY > > The primary PLL is what drives the CPU clk, except for times > when we are reprogramming the PLL itself (for rate changes) when > we temporarily switch to an alternate PLL. A subsequent patch adds > support to switch between primary and alternate PLL during rate > changes. > > The primary PLL operates on a single VCO range, between 600MHz > and 3GHz. However the CPUs do support OPPs with frequencies > between 300MHz and 600MHz. In order to support running the CPUs > at those frequencies we end up having to lock the PLL at twice > the rate and drive the CPU clk via the PLL/2 output and SMUX. > > So for frequencies above 600MHz we follow the following path > Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk > and for frequencies between 300MHz and 600MHz we follow > Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk > Support for this is added in a subsequent patch as well. > > ACD stands for Adaptive Clock Distribution and is used to > detect voltage droops. We do not add support for ACD as yet. > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > --- > drivers/clk/clk-fixed-factor.c | 2 +- > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clk-alpha-pll.h | 6 + > drivers/clk/qcom/clk-cpu-8996.c | 412 +++++++++++++++++++++++++++++++++++++++ > 5 files changed, 429 insertions(+), 1 deletion(-) > create mode 100644 drivers/clk/qcom/clk-cpu-8996.c > > diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c > index a5d402d..8e39bda 100644 > --- a/drivers/clk/clk-fixed-factor.c > +++ b/drivers/clk/clk-fixed-factor.c > @@ -94,7 +94,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, > init.num_parents = 1; > > hw = &fix->hw; > - ret = clk_hw_register(dev, hw); > + ret = devm_clk_hw_register(dev, hw); This should probably go in its own separate patch. > if (ret) { > kfree(fix); > hw = ERR_PTR(ret); > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index e42e1af..866ce1f 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -33,6 +33,15 @@ config QCOM_CLK_APCS_MSM8916 > Say Y if you want to support CPU frequency scaling on devices > such as msm8916. > > +config QCOM_CLK_APCC_MSM8996 > + tristate "MSM8996 CPU Clock Controller" > + depends on COMMON_CLK_QCOM > + select QCOM_KRYO_L2_ACCESSORS > + help > + Support for the CPU clock controller on msm8996 devices. > + Say Y if you want to support CPU clock scaling using CPUfreq > + drivers for dyanmic power management. > + > config QCOM_CLK_RPM > tristate "RPM based Clock Controller" > depends on COMMON_CLK_QCOM && MFD_QCOM_RPM > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 7c09ab1..a822fc8 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -36,6 +36,7 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o > obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o > obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o > obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o > +obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o > obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o > obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o > obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h > index f981b48..9ce2a32 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.h > +++ b/drivers/clk/qcom/clk-alpha-pll.h > @@ -50,6 +50,12 @@ struct pll_vco { > u32 val; > }; > > +#define VCO(a, b, c) { \ > + .val = a,\ > + .min_freq = b,\ > + .max_freq = c,\ > +} > + > /** > * struct clk_alpha_pll - phase locked loop (PLL) > * @offset: base address of registers > diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c > new file mode 100644 > index 0000000..beb97eb > --- /dev/null > +++ b/drivers/clk/qcom/clk-cpu-8996.c > @@ -0,0 +1,412 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +/* > + * Each of the CPU clusters (Power and Perf) on msm8996 are > + * clocked via 2 PLLs, a primary and alternate. There are also > + * 2 Mux'es, a primary and secondary all connected together > + * as shown below > + * > + * +-------+ > + * XO | | > + * +------------------>0 | > + * | | > + * PLL/2 | SMUX +----+ > + * +------->1 | | > + * | | | | > + * | +-------+ | +-------+ > + * | +---->0 | > + * | | | > + * +---------------+ | +----------->1 | CPU clk > + * |Primary PLL +----+ PLL_EARLY | | +------> > + * | +------+-----------+ +------>2 PMUX | > + * +---------------+ | | | | > + * | +------+ | +-->3 | > + * +--^+ ACD +-----+ | +-------+ > + * +---------------+ +------+ | > + * |Alt PLL | | > + * | +---------------------------+ > + * +---------------+ PLL_EARLY > + * > + * The primary PLL is what drives the CPU clk, except for times > + * when we are reprogramming the PLL itself (for rate changes) when > + * we temporarily switch to an alternate PLL. A subsequent patch adds > + * support to switch between primary and alternate PLL during rate > + * changes. > + * > + * The primary PLL operates on a single VCO range, between 600MHz > + * and 3GHz. However the CPUs do support OPPs with frequencies > + * between 300MHz and 600MHz. In order to support running the CPUs > + * at those frequencies we end up having to lock the PLL at twice > + * the rate and drive the CPU clk via the PLL/2 output and SMUX. > + * > + * So for frequencies above 600MHz we follow the following path > + * Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk > + * and for frequencies between 300MHz and 600MHz we follow > + * Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk > + * Support for this is added in a subsequent patch as well. > + * > + * ACD stands for Adaptive Clock Distribution and is used to > + * detect voltage droops. We do not add support for ACD as yet. > + */ > + > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > + > +#include "clk-alpha-pll.h" > +#include "clk-regmap.h" > + > +enum _pmux_input { > + DIV_2_INDEX = 0, > + PLL_INDEX, > + ACD_INDEX, > + ALT_INDEX, > + NUM_OF_PMUX_INPUTS > +}; > + > +static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { > + [PLL_OFF_L_VAL] = 0x04, > + [PLL_OFF_ALPHA_VAL] = 0x08, > + [PLL_OFF_USER_CTL] = 0x10, > + [PLL_OFF_CONFIG_CTL] = 0x18, > + [PLL_OFF_CONFIG_CTL_U] = 0x1c, > + [PLL_OFF_TEST_CTL] = 0x20, > + [PLL_OFF_TEST_CTL_U] = 0x24, > + [PLL_OFF_STATUS] = 0x28, > +}; > + > +static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = { > + [PLL_OFF_L_VAL] = 0x04, > + [PLL_OFF_ALPHA_VAL] = 0x08, > + [PLL_OFF_ALPHA_VAL_U] = 0x0c, > + [PLL_OFF_USER_CTL] = 0x10, > + [PLL_OFF_USER_CTL_U] = 0x14, > + [PLL_OFF_CONFIG_CTL] = 0x18, > + [PLL_OFF_TEST_CTL] = 0x20, > + [PLL_OFF_TEST_CTL_U] = 0x24, > + [PLL_OFF_STATUS] = 0x28, > +}; > + > +/* PLLs */ > + > +static const struct alpha_pll_config hfpll_config = { > + .l = 60, > + .config_ctl_val = 0x200d4828, > + .config_ctl_hi_val = 0x006, > + .pre_div_mask = BIT(12), > + .post_div_mask = 0x3 << 8, > + .main_output_mask = BIT(0), > + .early_output_mask = BIT(3), > +}; > + > +static struct clk_alpha_pll perfcl_pll = { > + .offset = 0x80000, > + .regs = prim_pll_regs, > + .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "perfcl_pll", > + .parent_names = (const char *[]){ "xo" }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_huayra_ops, > + }, > +}; > + > +static struct clk_alpha_pll pwrcl_pll = { > + .offset = 0x0, > + .regs = prim_pll_regs, > + .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "pwrcl_pll", > + .parent_names = (const char *[]){ "xo" }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_huayra_ops, > + }, > +}; > + > +static const struct pll_vco alt_pll_vco_modes[] = { > + VCO(3, 250000000, 500000000), > + VCO(2, 500000000, 750000000), > + VCO(1, 750000000, 1000000000), > + VCO(0, 1000000000, 2150400000), > +}; > + > +static const struct alpha_pll_config altpll_config = { > + .l = 16, > + .vco_val = 0x3 << 20, > + .vco_mask = 0x3 << 20, > + .config_ctl_val = 0x4001051b, > + .post_div_mask = 0x3 << 8, > + .post_div_val = 0x1, > + .main_output_mask = BIT(0), > + .early_output_mask = BIT(3), > +}; > + > +static struct clk_alpha_pll perfcl_alt_pll = { > + .offset = 0x80100, > + .regs = alt_pll_regs, > + .vco_table = alt_pll_vco_modes, > + .num_vco = ARRAY_SIZE(alt_pll_vco_modes), > + .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "perfcl_alt_pll", > + .parent_names = (const char *[]){ "xo" }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_hwfsm_ops, > + }, > +}; > + > +static struct clk_alpha_pll pwrcl_alt_pll = { > + .offset = 0x100, > + .regs = alt_pll_regs, > + .vco_table = alt_pll_vco_modes, > + .num_vco = ARRAY_SIZE(alt_pll_vco_modes), > + .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "pwrcl_alt_pll", > + .parent_names = (const char *[]){ "xo" }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_hwfsm_ops, > + }, > +}; > + > +/* Mux'es */ > + > +struct clk_cpu_8996_mux { > + u32 reg; > + u8 shift; > + u8 width; > + struct clk_hw *pll; > + struct clk_regmap clkr; > +}; > + > +static inline > +struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw) > +{ > + return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr); > +} > + > +static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw) > +{ > + u32 val; > + struct clk_regmap *clkr = to_clk_regmap(hw); > + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); > + u32 mask = (u32)GENMASK(cpuclk->width - 1, 0); > + > + regmap_read(clkr->regmap, cpuclk->reg, &val); > + val >>= (u32)(cpuclk->shift); > + > + return (u8)(val & mask); > +} > + > +static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) > +{ > + u32 val; > + struct clk_regmap *clkr = to_clk_regmap(hw); > + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); > + unsigned int mask = GENMASK(cpuclk->width + cpuclk->shift - 1, > + cpuclk->shift); > + > + val = (u32)index; > + val <<= (u32)(cpuclk->shift); > + > + return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val); > +} > + > +static int > +clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) > +{ > + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); > + struct clk_hw *parent = cpuclk->pll; > + > + req->best_parent_rate = clk_hw_round_rate(parent, req->rate); > + req->best_parent_hw = parent; > + > + return 0; > +} > + > +const struct clk_ops clk_cpu_8996_mux_ops = { > + .set_parent = clk_cpu_8996_mux_set_parent, > + .get_parent = clk_cpu_8996_mux_get_parent, > + .determine_rate = clk_cpu_8996_mux_determine_rate, > +}; > + > +static struct clk_cpu_8996_mux pwrcl_smux = { > + .reg = 0x40, > + .shift = 2, > + .width = 2, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "pwrcl_smux", > + .parent_names = (const char *[]){ > + "xo", > + "pwrcl_pll_main", > + }, > + .num_parents = 2, > + .ops = &clk_cpu_8996_mux_ops, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_cpu_8996_mux perfcl_smux = { > + .reg = 0x80040, > + .shift = 2, > + .width = 2, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "perfcl_smux", > + .parent_names = (const char *[]){ > + "xo", > + "perfcl_pll_main", > + }, > + .num_parents = 2, > + .ops = &clk_cpu_8996_mux_ops, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_cpu_8996_mux pwrcl_pmux = { > + .reg = 0x40, > + .shift = 0, > + .width = 2, > + .pll = &pwrcl_pll.clkr.hw, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "pwrcl_pmux", > + .parent_names = (const char *[]){ > + "pwrcl_smux", > + "pwrcl_pll", > + "pwrcl_pll_acd", > + "pwrcl_alt_pll", > + }, > + .num_parents = 4, > + .ops = &clk_cpu_8996_mux_ops, > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > + }, > +}; > + > +static struct clk_cpu_8996_mux perfcl_pmux = { > + .reg = 0x80040, > + .shift = 0, > + .width = 2, > + .pll = &perfcl_pll.clkr.hw, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "perfcl_pmux", > + .parent_names = (const char *[]){ > + "perfcl_smux", > + "perfcl_pll", > + "perfcl_pll_acd", > + "perfcl_alt_pll", > + }, > + .num_parents = 4, > + .ops = &clk_cpu_8996_mux_ops, > + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > + }, > +}; > + > +static const struct regmap_config cpu_msm8996_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x80210, > + .fast_io = true, > + .val_format_endian = REGMAP_ENDIAN_LITTLE, > +}; > + > +struct clk_regmap *clks[] = { > + &perfcl_pll.clkr, > + &pwrcl_pll.clkr, > + &perfcl_alt_pll.clkr, > + &pwrcl_alt_pll.clkr, > + &perfcl_smux.clkr, > + &pwrcl_smux.clkr, > + &perfcl_pmux.clkr, > + &pwrcl_pmux.clkr, > +}; > + > +static int > +qcom_cpu_clk_msm8996_register_clks(struct device *dev, struct regmap *regmap) > +{ > + int i, ret; > + > + perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main", > + "perfcl_pll", > + CLK_SET_RATE_PARENT, 1, 2); > + > + pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main", > + "pwrcl_pll", > + CLK_SET_RATE_PARENT, 1, 2); > + > + for (i = 0; i < ARRAY_SIZE(clks); i++) { > + ret = devm_clk_register_regmap(dev, clks[i]); > + if (ret) > + return ret; > + } > + > + clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config); > + clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config); > + clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config); > + clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config); > + > + return ret; > +} > + > +static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev) > +{ > + int ret; > + void __iomem *base; > + struct resource *res; > + struct regmap *regmap; > + struct clk_hw_onecell_data *data; > + struct device *dev = &pdev->dev; > + > + data = devm_kzalloc(dev, sizeof(*data) + 2 * sizeof(struct clk_hw *), > + GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + base = devm_ioremap_resource(dev, res); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap); > + if (ret) > + return ret; > + > + data->hws[0] = &pwrcl_pmux.clkr.hw; > + data->hws[1] = &perfcl_pmux.clkr.hw; > + data->num = 2; > + > + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data); > +} > + > +static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = { > + { .compatible = "qcom,msm8996-apcc" }, > + {} > +}; > + > +static struct platform_driver qcom_cpu_clk_msm8996_driver = { > + .probe = qcom_cpu_clk_msm8996_driver_probe, > + .driver = { > + .name = "qcom-msm8996-apcc", > + .of_match_table = qcom_cpu_clk_msm8996_match_table, > + }, > +}; > +module_platform_driver(qcom_cpu_clk_msm8996_driver); > + > +MODULE_ALIAS("platform:msm8996-apcc"); > +MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver"); > +MODULE_LICENSE("GPL v2"); > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 16-05-18, 16:12, Amit Kucheria wrote: > > + ret = PTR_ERR_OR_ZERO(opp_temp = > > + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > > + if (0 > ret) > > Any particular reason to prefer this over (ret < 0) that is generally > used? I've seen it used to avoid the == vs. = typos, but not for other > comparisons. > > Suggest sticking to what is commonly used i.e. ret < 0. > > > + goto free_opp; > > + > > + cpu_dev = get_cpu_device(GOLD_LEAD); > > Error check cpu_dev here? > > > + ret = PTR_ERR_OR_ZERO(opp_temp = > > + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > > + if (0 > ret) > > + goto free_opp; The goto here is wrong > > + > > + > > + ret = PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq-dt", > > + -1, NULL, 0)); > > + > > + if (0 == ret) > > + return 0; > > + > > +free_opp: > > + dev_pm_opp_put_supported_hw(opp_temp); > > This is not needed because dev_pm_opp_set_supported_hw will free > memory in case of failure. This call in only needed in case of a > successful get. But this is still required for the case where platform device registration fails.
On Wed, May 16, 2018 at 5:11 PM, Viresh Kumar <viresh.kumar@linaro.org> wrote: > On 16-05-18, 16:12, Amit Kucheria wrote: >> > + ret = PTR_ERR_OR_ZERO(opp_temp = >> > + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); >> > + if (0 > ret) >> >> Any particular reason to prefer this over (ret < 0) that is generally >> used? I've seen it used to avoid the == vs. = typos, but not for other >> comparisons. >> >> Suggest sticking to what is commonly used i.e. ret < 0. >> >> > + goto free_opp; >> > + >> > + cpu_dev = get_cpu_device(GOLD_LEAD); >> >> Error check cpu_dev here? >> >> > + ret = PTR_ERR_OR_ZERO(opp_temp = >> > + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); >> > + if (0 > ret) >> > + goto free_opp; > > The goto here is wrong > >> > + >> > + >> > + ret = PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq-dt", >> > + -1, NULL, 0)); >> > + >> > + if (0 == ret) >> > + return 0; >> > + >> > +free_opp: >> > + dev_pm_opp_put_supported_hw(opp_temp); >> >> This is not needed because dev_pm_opp_set_supported_hw will free >> memory in case of failure. This call in only needed in case of a >> successful get. > > But this is still required for the case where platform device > registration fails. Agreed. The overall error path needs to be re-written with proper check of return values. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: amit.kucheria@verdurent.com <amit.kucheria@verdurent.com> On > Behalf Of Amit Kucheria > Sent: Wednesday, May 16, 2018 16:13 > To: Ilia Lin <ilialin@codeaurora.org> > Cc: Michael Turquette <mturquette@baylibre.com>; sboyd@kernel.org; Rob > Herring <robh@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Viresh > Kumar <viresh.kumar@linaro.org>; nm@ti.com; lgirdwood@gmail.com; > broonie@kernel.org; Andy Gross <andy.gross@linaro.org>; David Brown > <david.brown@linaro.org>; catalin.marinas@arm.com; > will.deacon@arm.com; Rafael J. Wysocki <rjw@rjwysocki.net>; linux- > clk@vger.kernel.org; devicetree@vger.kernel.org; LKML <linux- > kernel@vger.kernel.org>; Linux PM list <linux-pm@vger.kernel.org>; linux- > arm-msm@vger.kernel.org; linux-soc@vger.kernel.org; lakml <linux-arm- > kernel@lists.infradead.org>; Rajendra Nayak <rnayak@codeaurora.org>; > nicolas.dechesne@linaro.org; celster@codeaurora.org; > tfinkel@codeaurora.org > Subject: Re: [PATCH v7 12/14] cpufreq: Add Kryo CPU scaling driver > > On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote: > > In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO > > processors, the CPU ferequencies subset and voltage value of each OPP > > varies > > s/ferequencies/frequency > > > based on the silicon variant in use. Qualcomm Process Voltage Scaling > > Tables defines the voltage and frequency value based on the msm-id in > > SMEM and speedbin blown in the efuse combination. > > The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the > > SoC to provide the OPP framework with required information. > > This is used to determine the voltage and frequency value for each OPP > > of > > operating-points-v2 table when it is parsed by the OPP framework. > > > > Signed-off-by: Ilia Lin <ilialin@codeaurora.org> > > --- > > drivers/cpufreq/Kconfig.arm | 11 +++ > > drivers/cpufreq/Makefile | 1 + > > drivers/cpufreq/cpufreq-dt-platdev.c | 3 + > > drivers/cpufreq/qcom-cpufreq-kryo.c | 150 > > +++++++++++++++++++++++++++++++++++ > > 4 files changed, 165 insertions(+) > > create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c > > > > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm > > index de55c7d..5c16f05 100644 > > --- a/drivers/cpufreq/Kconfig.arm > > +++ b/drivers/cpufreq/Kconfig.arm > > @@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ > > depends on ARCH_OMAP2PLUS > > default ARCH_OMAP2PLUS > > > > +config ARM_QCOM_CPUFREQ_KRYO > > + bool "Qualcomm Technologies, Inc. Kryo based CPUFreq" > > "Qualcomm Kryo CPUFreq support" should be enough. Kconfig isn't the place > for Trademark compliance :-) This is mandatory requirement of the QTIs legal. > > > + depends on QCOM_QFPROM > > + depends on QCOM_SMEM > > + select PM_OPP > > + help > > + This adds the CPUFreq driver for > > + Qualcomm Technologies, Inc. Kryo SoC based boards. > > + > > + If in doubt, say N. > > + > > config ARM_S3C_CPUFREQ > > bool > > help > > diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index > > 8d24ade..fb4a2ec 100644 > > --- a/drivers/cpufreq/Makefile > > +++ b/drivers/cpufreq/Makefile > > @@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu- > cpufreq.o > > obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o > > obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o > > obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o > > +obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o > > obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o > > obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o > > obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o > > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c > > b/drivers/cpufreq/cpufreq-dt-platdev.c > > index 3b585e4..77d6ab8 100644 > > --- a/drivers/cpufreq/cpufreq-dt-platdev.c > > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c > > @@ -118,6 +118,9 @@ > > > > { .compatible = "nvidia,tegra124", }, > > > > + { .compatible = "qcom,apq8096", }, > > + { .compatible = "qcom,msm8996", }, > > + > > { .compatible = "st,stih407", }, > > { .compatible = "st,stih410", }, > > > > diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c > > b/drivers/cpufreq/qcom-cpufreq-kryo.c > > new file mode 100644 > > index 0000000..10d7236 > > --- /dev/null > > +++ b/drivers/cpufreq/qcom-cpufreq-kryo.c > > @@ -0,0 +1,150 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > Stray space here. > > > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > > + * > > + * This program is free software; you can redistribute it and/or > > + modify > > + * it under the terms of the GNU General Public License version 2 and > > + * only version 2 as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > +#include <linux/cpu.h> > > +#include <linux/err.h> > > +#include <linux/init.h> > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/nvmem-consumer.h> > > +#include <linux/of.h> > > +#include <linux/platform_device.h> > > +#include <linux/pm_opp.h> > > +#include <linux/slab.h> > > +#include <linux/soc/qcom/smem.h> > > + > > +#define MSM_ID_SMEM 137 > > +#define SILVER_LEAD 0 > > +#define GOLD_LEAD 2 > > + > > +enum _msm_id { > > + MSM8996V3 = 0xF6ul, > > + APQ8096V3 = 0x123ul, > > + MSM8996SG = 0x131ul, > > + APQ8096SG = 0x138ul, > > +}; > > + > > +enum _msm8996_version { > > + MSM8996_V3, > > + MSM8996_SG, > > + NUM_OF_MSM8996_VERSIONS, > > +}; > > + > > +static enum _msm8996_version __init > > +qcom_cpufreq_kryo_get_msm_id(void) > > +{ > > + size_t len; > > + u32 *msm_id; > > + enum _msm8996_version version; > > + > > + msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, > MSM_ID_SMEM, &len); > > + /* The first 4 bytes are format, next to them is the actual msm-id */ > > + msm_id++; > > + > > + switch ((enum _msm_id)*msm_id) { > > + case MSM8996V3: > > + case APQ8096V3: > > + version = MSM8996_V3; > > + break; > > + case MSM8996SG: > > + case APQ8096SG: > > + version = MSM8996_SG; > > + break; > > + default: > > + version = NUM_OF_MSM8996_VERSIONS; > > + } > > + > > + return version; > > +} > > + > > +static int __init qcom_cpufreq_kryo_driver_init(void) > > +{ > > + size_t len; > > + int ret; > > + u32 versions; > > + enum _msm8996_version msm8996_version; > > + u8 *speedbin; > > + struct device *cpu_dev; > > + struct device_node *np; > > + struct nvmem_cell *speedbin_nvmem; > > + struct opp_table *opp_temp = NULL; > > + > > + cpu_dev = get_cpu_device(SILVER_LEAD); > > + if (IS_ERR_OR_NULL(cpu_dev)) > > + return PTR_ERR(cpu_dev); > > + > > + msm8996_version = qcom_cpufreq_kryo_get_msm_id(); > > + if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { > > + dev_err(cpu_dev, "Not Snapdragon 820/821!"); > > + return -ENODEV; > > + } > > Use tab instead of spaces. > > > + > > + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); > > + if (IS_ERR_OR_NULL(np)) > > + return PTR_ERR(np); > > + > > + if (!of_device_is_compatible(np, "operating-points-v2-kryo-cpu")) { > > + ret = -ENOENT; > > + goto free_np; > > + } > > + > > + speedbin_nvmem = of_nvmem_cell_get(np, NULL); > > + if (IS_ERR(speedbin_nvmem)) { > > + ret = PTR_ERR(speedbin_nvmem); > > + dev_err(cpu_dev, "Could not get nvmem cell: %d\n", ret); > > + goto free_np; > > + } > > + > > + speedbin = nvmem_cell_read(speedbin_nvmem, &len); > > + > > + switch (msm8996_version) { > > + case MSM8996_V3: > > + versions = 1 << (unsigned int)(*speedbin); > > + break; > > + case MSM8996_SG: > > + versions = 1 << ((unsigned int)(*speedbin) + 4); > > + break; > > + default: > > + BUG(); > > + break; > > + } > > + > > + ret = PTR_ERR_OR_ZERO(opp_temp = > > + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > > + if (0 > ret) > > Any particular reason to prefer this over (ret < 0) that is generally used? I've > seen it used to avoid the == vs. = typos, but not for other comparisons. > > Suggest sticking to what is commonly used i.e. ret < 0. > > > + goto free_opp; > > + > > + cpu_dev = get_cpu_device(GOLD_LEAD); > > Error check cpu_dev here? > > > + ret = PTR_ERR_OR_ZERO(opp_temp = > > + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > > + if (0 > ret) > > + goto free_opp; > > + > > + > > + ret = PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq- > dt", > > + -1, > > + NULL, 0)); > > + > > + if (0 == ret) > > + return 0; > > + > > +free_opp: > > + dev_pm_opp_put_supported_hw(opp_temp); > > This is not needed because dev_pm_opp_set_supported_hw will free > memory in case of failure. This call in only needed in case of a successful get. > > > + > > +free_np: > > + of_node_put(np); > > + return ret; > > > Suggest something like this instead: > > . > . > > opp_temp = dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > if (IS_ERR(opp_temp)) { > dev_err(cpu_dev, "Failed to set supported hardware\n"); > ret = PTR_ERR(opp_temp); > goto free_np; > } > > cpu_dev = get_cpu_device(GOLD_LEAD); > > opp_temp = dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > if (IS_ERR(opp_temp)) { > dev_err(cpu_dev, "Failed to set supported hardware\n"); > ret = PTR_ERR(opp_temp); > goto free_np; > } > > ret = platform_device_register_simple("cpufreq-dt", -1, NULL, 0)); > > if (!IS_ERR_OR_NULL(ret)) > goto out; > > free_np: > of_node_put(np); > out: > return ret; > > > +} > > +late_initcall(qcom_cpufreq_kryo_driver_init); > > + > > +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq > > +driver"); MODULE_LICENSE("GPL v2"); > > -- > > 1.9.1 > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: Viresh Kumar <viresh.kumar@linaro.org> > Sent: Wednesday, May 16, 2018 17:12 > To: Amit Kucheria <amit.kucheria@linaro.org> > Cc: Ilia Lin <ilialin@codeaurora.org>; Michael Turquette > <mturquette@baylibre.com>; sboyd@kernel.org; Rob Herring > <robh@kernel.org>; Mark Rutland <mark.rutland@arm.com>; nm@ti.com; > lgirdwood@gmail.com; broonie@kernel.org; Andy Gross > <andy.gross@linaro.org>; David Brown <david.brown@linaro.org>; > catalin.marinas@arm.com; will.deacon@arm.com; Rafael J. Wysocki > <rjw@rjwysocki.net>; linux-clk@vger.kernel.org; > devicetree@vger.kernel.org; LKML <linux-kernel@vger.kernel.org>; Linux > PM list <linux-pm@vger.kernel.org>; linux-arm-msm@vger.kernel.org; linux- > soc@vger.kernel.org; lakml <linux-arm-kernel@lists.infradead.org>; > Rajendra Nayak <rnayak@codeaurora.org>; nicolas.dechesne@linaro.org; > celster@codeaurora.org; tfinkel@codeaurora.org > Subject: Re: [PATCH v7 12/14] cpufreq: Add Kryo CPU scaling driver > > On 16-05-18, 16:12, Amit Kucheria wrote: > > > + ret = PTR_ERR_OR_ZERO(opp_temp = > > > + > dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > > > + if (0 > ret) > > > > Any particular reason to prefer this over (ret < 0) that is generally > > used? I've seen it used to avoid the == vs. = typos, but not for other > > comparisons. > > > > Suggest sticking to what is commonly used i.e. ret < 0. > > > > > + goto free_opp; > > > + > > > + cpu_dev = get_cpu_device(GOLD_LEAD); > > > > Error check cpu_dev here? > > > > > + ret = PTR_ERR_OR_ZERO(opp_temp = > > > + > dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > > > + if (0 > ret) > > > + goto free_opp; > > The goto here is wrong If we are here, then the first dev_pm_opp_set_supported_hw() succeeded. And should be deallocated before exit with error. > > > > + > > > + > > > + ret = > PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq-dt", > > > + -1, > > > + NULL, 0)); > > > + > > > + if (0 == ret) > > > + return 0; > > > + > > > +free_opp: > > > + dev_pm_opp_put_supported_hw(opp_temp); > > > > This is not needed because dev_pm_opp_set_supported_hw will free > > memory in case of failure. This call in only needed in case of a > > successful get. > > But this is still required for the case where platform device registration fails. > > -- > viresh -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
> -----Original Message----- > From: ilialin@codeaurora.org <ilialin@codeaurora.org> > Sent: Thursday, May 17, 2018 10:51 > To: 'Viresh Kumar' <viresh.kumar@linaro.org>; 'Amit Kucheria' > <amit.kucheria@linaro.org> > Cc: 'Michael Turquette' <mturquette@baylibre.com>; 'sboyd@kernel.org' > <sboyd@kernel.org>; 'Rob Herring' <robh@kernel.org>; 'Mark Rutland' > <mark.rutland@arm.com>; 'nm@ti.com' <nm@ti.com>; > 'lgirdwood@gmail.com' <lgirdwood@gmail.com>; 'broonie@kernel.org' > <broonie@kernel.org>; 'Andy Gross' <andy.gross@linaro.org>; 'David Brown' > <david.brown@linaro.org>; 'catalin.marinas@arm.com' > <catalin.marinas@arm.com>; 'will.deacon@arm.com' > <will.deacon@arm.com>; 'Rafael J. Wysocki' <rjw@rjwysocki.net>; 'linux- > clk@vger.kernel.org' <linux-clk@vger.kernel.org>; > 'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'LKML' <linux- > kernel@vger.kernel.org>; 'Linux PM list' <linux-pm@vger.kernel.org>; 'linux- > arm-msm@vger.kernel.org' <linux-arm-msm@vger.kernel.org>; 'linux- > soc@vger.kernel.org' <linux-soc@vger.kernel.org>; 'lakml' <linux-arm- > kernel@lists.infradead.org>; 'Rajendra Nayak' <rnayak@codeaurora.org>; > 'nicolas.dechesne@linaro.org' <nicolas.dechesne@linaro.org>; > 'celster@codeaurora.org' <celster@codeaurora.org>; > 'tfinkel@codeaurora.org' <tfinkel@codeaurora.org> > Subject: RE: [PATCH v7 12/14] cpufreq: Add Kryo CPU scaling driver > > > > > -----Original Message----- > > From: Viresh Kumar <viresh.kumar@linaro.org> > > Sent: Wednesday, May 16, 2018 17:12 > > To: Amit Kucheria <amit.kucheria@linaro.org> > > Cc: Ilia Lin <ilialin@codeaurora.org>; Michael Turquette > > <mturquette@baylibre.com>; sboyd@kernel.org; Rob Herring > > <robh@kernel.org>; Mark Rutland <mark.rutland@arm.com>; nm@ti.com; > > lgirdwood@gmail.com; broonie@kernel.org; Andy Gross > > <andy.gross@linaro.org>; David Brown <david.brown@linaro.org>; > > catalin.marinas@arm.com; will.deacon@arm.com; Rafael J. Wysocki > > <rjw@rjwysocki.net>; linux-clk@vger.kernel.org; > > devicetree@vger.kernel.org; LKML <linux-kernel@vger.kernel.org>; Linux > > PM list <linux-pm@vger.kernel.org>; linux-arm-msm@vger.kernel.org; > > linux- soc@vger.kernel.org; lakml > > <linux-arm-kernel@lists.infradead.org>; > > Rajendra Nayak <rnayak@codeaurora.org>; nicolas.dechesne@linaro.org; > > celster@codeaurora.org; tfinkel@codeaurora.org > > Subject: Re: [PATCH v7 12/14] cpufreq: Add Kryo CPU scaling driver > > > > On 16-05-18, 16:12, Amit Kucheria wrote: > > > > + ret = PTR_ERR_OR_ZERO(opp_temp = > > > > + > > dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > > > > + if (0 > ret) > > > > > > Any particular reason to prefer this over (ret < 0) that is > > > generally used? I've seen it used to avoid the == vs. = typos, but > > > not for other comparisons. > > > > > > Suggest sticking to what is commonly used i.e. ret < 0. > > > > > > > + goto free_opp; > > > > + > > > > + cpu_dev = get_cpu_device(GOLD_LEAD); > > > > > > Error check cpu_dev here? > > > > > > > + ret = PTR_ERR_OR_ZERO(opp_temp = > > > > + > > dev_pm_opp_set_supported_hw(cpu_dev,&versions,1)); > > > > + if (0 > ret) > > > > + goto free_opp; > > > > The goto here is wrong > > If we are here, then the first dev_pm_opp_set_supported_hw() succeeded. > And should be deallocated before exit with error. My bad. Got you. > > > > > > > + > > > > + > > > > + ret = > > PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq-dt", > > > > + -1, > > > > + NULL, 0)); > > > > + > > > > + if (0 == ret) > > > > + return 0; > > > > + > > > > +free_opp: > > > > + dev_pm_opp_put_supported_hw(opp_temp); > > > > > > This is not needed because dev_pm_opp_set_supported_hw will free > > > memory in case of failure. This call in only needed in case of a > > > successful get. > > > > But this is still required for the case where platform device registration fails. > > > > -- > > viresh -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html