Message ID | 20180314143529.1456168-1-arnd@arndb.de |
---|---|
Headers | show |
Series | remove eight obsolete architectures | expand |
Do we have anything left that still implements NOMMU? David -- To unsubscribe from this list: send the line "unsubscribe linux-pwm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi David,
On Thu, Mar 15, 2018 at 10:42 AM, David Howells <dhowells@redhat.com> wrote:
> Do we have anything left that still implements NOMMU?
Sure: arm, c6x, m68k, microblaze, and sh.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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On Thu, Mar 15, 2018 at 10:42 AM, David Howells <dhowells@redhat.com> wrote:
> Do we have anything left that still implements NOMMU?
Yes, plenty. I was wondering the same thing, but it seems that the architectures
we remove are almost completely representative of what we support overall,
except that they are all not licensed to 3rd parties, unlike many of the ones we
keep.
I've made an overview of the remaining architectures for my own reference[1].
The remaining NOMMU architectures are:
- arch/arm has ARMv7-M (Cortex-M microcontroller), which is actually
gaining traction
- arch/sh has an open-source J2 core that was added not that long ago,
it seems to
be the only SH compatible core that anyone is working on.
- arch/microblaze supports both MMU/NOMMU modes (most use an MMU)
- arch/m68k supports several NOMMU targets, both the coldfire SoCs and the
classic processors
- c6x has no MMU
Arnd
[1] https://docs.google.com/spreadsheets/d/1QxMvW5jpVG2jb4RM9CQQl27-wVpNYOa-_3K2RVKifb0
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On 03/15/2018 10:42 AM, David Howells wrote: > Do we have anything left that still implements NOMMU? > RISC-V ? (evil grin :-) Cheers, Hannes
On Thu, Mar 15, 2018 at 10:59 AM, Hannes Reinecke <hare@suse.de> wrote: > On 03/15/2018 10:42 AM, David Howells wrote: >> Do we have anything left that still implements NOMMU? >> > RISC-V ? > (evil grin :-) Is anyone producing a chip that includes enough of the Privileged ISA spec to have things like system calls, but not the MMU parts? I thought at least initially the kernel only supports hardware that has a rather complete feature set. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-pwm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Mar 15, 2018 at 11:42:25AM +0100, Arnd Bergmann wrote: > Is anyone producing a chip that includes enough of the Privileged ISA spec > to have things like system calls, but not the MMU parts? Various SiFive SOCs seem to support M and U mode, but no S mode or iommu. That should be enough for nommu Linux running in M mode if someone cares enough to actually port it. -- To unsubscribe from this list: send the line "unsubscribe linux-pwm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On Thu, Mar 15, 2018 at 10:56:48AM +0100, Arnd Bergmann wrote: > On Thu, Mar 15, 2018 at 10:42 AM, David Howells <dhowells@redhat.com> wrote: > > Do we have anything left that still implements NOMMU? Please don't kill !MMU. > Yes, plenty. > I've made an overview of the remaining architectures for my own reference[1]. > The remaining NOMMU architectures are: > > - arch/arm has ARMv7-M (Cortex-M microcontroller), which is actually > gaining traction ARMv7-R as well, also seems ARM is coming up with more !MMU's - v8-M, v8-R. In addition, though only of academic interest, ARM MMU capable platform's can run !MMU Linux. afzal > - arch/sh has an open-source J2 core that was added not that long ago, > it seems to > be the only SH compatible core that anyone is working on. > - arch/microblaze supports both MMU/NOMMU modes (most use an MMU) > - arch/m68k supports several NOMMU targets, both the coldfire SoCs and the > classic processors > - c6x has no MMU -- To unsubscribe from this list: send the line "unsubscribe linux-pwm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, 15 Mar 2018 03:42:25 PDT (-0700), Arnd Bergmann wrote: > On Thu, Mar 15, 2018 at 10:59 AM, Hannes Reinecke <hare@suse.de> wrote: >> On 03/15/2018 10:42 AM, David Howells wrote: >>> Do we have anything left that still implements NOMMU? >>> >> RISC-V ? >> (evil grin :-) > > Is anyone producing a chip that includes enough of the Privileged ISA spec > to have things like system calls, but not the MMU parts? > > I thought at least initially the kernel only supports hardware that has a rather > complete feature set. We currently do not have a NOMMU port. As far as I know, everyone who's currently producing RISC-V hardware with enough memory to run Linux has S mode with paging support. The ISA allows for S mode without paging but there's no hardware for that -- if you're going to put a DRAM controller on there then paging seems pretty cheap. You could run a NOMMU port on a system with S-mode and paging, but With all the superpage stuff I don't think you'll get an appreciable performance win for any workload running without an MMU so there's nothing to justify the work (and incompatibility) of a NOMMU port there. While I think you could implement a NOMMU port on a machine with only M and U modes (and therefor no address translation at all), I don't know of any MU-only machines that have enough memory to run Linux (ours have less than 32KiB). A SBI-free Linux would be a prerequisite for this, but there's some interest in that outside of a NOMMU port so it might materialize anyway. Of course, QEMU could probably be tricked into emulating one of these machines with little to no effort :)... That said, I doubt we'll see a NOMMU port materialize without some real hardware as it's a lot of work for a QEMU-only target. -- To unsubscribe from this list: send the line "unsubscribe linux-pwm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html