Message ID | 20171012183247.23679-1-ard.biesheuvel@linaro.org |
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Headers | show
Return-Path: <devicetree-owner@vger.kernel.org> X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="RLzSvZSC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yCfbz5BTPz9sPm for <incoming-dt@patchwork.ozlabs.org>; Fri, 13 Oct 2017 05:33:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755606AbdJLSdB (ORCPT <rfc822;incoming-dt@patchwork.ozlabs.org>); Thu, 12 Oct 2017 14:33:01 -0400 Received: from mail-wm0-f52.google.com ([74.125.82.52]:51497 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755596AbdJLSc7 (ORCPT <rfc822; devicetree@vger.kernel.org>); Thu, 12 Oct 2017 14:32:59 -0400 Received: by mail-wm0-f52.google.com with SMTP id f4so15777011wme.0 for <devicetree@vger.kernel.org>; Thu, 12 Oct 2017 11:32:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=WcLVmRr1DEZoyASbIlPOQE1XJcj4GPTNuip+wgvnbKI=; b=RLzSvZSCLV0KC0k9WBnMr6v7nbzRUgLvQwY/PLMvP9JJ+pdJUm5T63hlbK2mSGpGY1 kQwPBUpzTxia+szVvWoIg3xZA01zxPgJ3ojdvYZZgIuCnP28UydYIPE3dXnvJPzEG4PH y4KiJJtoOLqNQAvUrtY9P0dYAPozSvy6gVA9s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WcLVmRr1DEZoyASbIlPOQE1XJcj4GPTNuip+wgvnbKI=; b=l9mzJjrHkFoFXTfy3uz30D/76pA8u19+ggtI+q5rB3RoGw9tZUxuQtwumDD5cvcorY MER01CRTRaPDmMJ6fIoCnGPFRC0GED1fFlX9dS5pePje5uaDmAYmBQRiHk3K2PI4F1i+ XuYI7lufOMfe4SjQ0wSn2wr1p7xKaUAmw/LPnDHPUb0l90inC4fC4UcbvvvzDdg/PgC2 SO16DcFDEhG5gVicav7JXrSybFUsvj5czXF1xWdPOQuE9Vgar+Irg2lfJYMtCMcw66jo brqQkBdku5yRfmgchQ6Jd8lxq1hvsz5RRG967v+PxRzQ1cbNYYOJF/YMpqIAav3WrYl1 BKvg== X-Gm-Message-State: AMCzsaVZ23hk95rKWW48xm81Z8bwYYCxvymevlqNdxGLapgtDJtc7cIP dT1PzCehFAhapdyD0+9udDY9ow== X-Google-Smtp-Source: AOwi7QDiyNd3GuCsKOIB1xcVbx2s5oyVwp2gz9gNUXeJVX74iAl2T5CYiNqly6AhVMuQ74+5OrgLgw== X-Received: by 10.223.184.140 with SMTP id i12mr2621049wrf.31.1507833178390; Thu, 12 Oct 2017 11:32:58 -0700 (PDT) Received: from localhost.localdomain ([196.78.24.219]) by smtp.gmail.com with ESMTPSA id i13sm14730579wre.93.2017.10.12.11.32.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Oct 2017 11:32:57 -0700 (PDT) From: Ard Biesheuvel <ard.biesheuvel@linaro.org> To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel <ard.biesheuvel@linaro.org> Subject: [PATCH v3 0/2] implement workaround for Socionext Synquacer pre-ITS Date: Thu, 12 Oct 2017 19:32:45 +0100 Message-Id: <20171012183247.23679-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: <devicetree.vger.kernel.org> X-Mailing-List: devicetree@vger.kernel.org |
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implement workaround for Socionext Synquacer pre-ITS
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>From patch 2/2: The Socionext Synquacer SoC's implementation of GICv3 has a so-called 'pre-ITS', which maps 32-bit writes targeted at a separate window of size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device ID taken from bits [device_id_bits + 1:2] of the window offset. Writes that target GITS_TRANSLATER directly are reported as originating from device ID #0. So add a workaround for this. Given that this breaks isolation, clear the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. v3: - add patch to pull device ID space discovery forward, so we can quirk it as well (as we already do for Cavium) - use existing quirks framework as much as possible - get rid of ITS_WORKAROUND_xxx flag: it is no longer needed after the refactoring v2: - use a 32-bit host address/size rather than a PCI address, to factor out the involvement of an SMMU (which the platform does have, but it is unclear atm if it can be exposed to the OS) - add msi_domain_flags member to move the quirk flag checks out of the common code path Ard Biesheuvel (2): drivers/irqchip: gicv3: probe device ID space before quirks handling drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 + arch/arm64/Kconfig | 8 ++ drivers/irqchip/irq-gic-v3-its.c | 81 ++++++++++++++++---- 3 files changed, 78 insertions(+), 15 deletions(-)