[0/5] arm64: dts: allwinner: a64: Enable deinterlace core
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Message ID 20200125110353.591658-1-jernej.skrabec@siol.net
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  • arm64: dts: allwinner: a64: Enable deinterlace core
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Jernej Skrabec Jan. 25, 2020, 11:03 a.m. UTC
Allwinner A64 contains deinterlace core, compatible to the one found in
H3. It can be used in combination with VPU to playback interlaced videos.

Please take a look.

Best regards,
Jernej

Jernej Skrabec (5):
  dt-bindings: interconnect: sunxi: Add A64 MBUS compatible
  clk: sunxi-ng: a64: Export MBUS clock
  arm64: dts: allwinner: a64: Add MBUS controller node
  media: dt-bindings: media: Add Allwinner A64 deinterlace compatible
  arm64: dts: allwinner: a64: Add deinterlace core node

 .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml   |  1 +
 .../media/allwinner,sun8i-h3-deinterlace.yaml |  6 ++++-
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 +++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun50i-a64.h         |  4 ----
 include/dt-bindings/clock/sun50i-a64-ccu.h    |  2 +-
 5 files changed, 29 insertions(+), 6 deletions(-)

Comments

Maxime Ripard Jan. 27, 2020, 2:59 p.m. UTC | #1
Hi,

On Sat, Jan 25, 2020 at 12:03:51PM +0100, Jernej Skrabec wrote:
> A64 contains MBUS, which is the bus used by DMA devices to access
> system memory.
>
> MBUS controller is responsible for arbitration between channels based
> on set priority and can do some other things as well, like report
> bandwidth used. It also maps RAM region to different address than CPU.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 862b47dc9dc9..d225ea1f3b87 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -1061,6 +1061,14 @@ pwm: pwm@1c21400 {
>  			status = "disabled";
>  		};
>
> +		mbus: dram-controller@1c62000 {
> +			compatible = "allwinner,sun50i-a64-mbus";
> +			reg = <0x01c62000 0x1000>;
> +			clocks = <&ccu CLK_MBUS>;

We're merging the clock header patch and the DT through two different
trees, so you can't use it right away. You should use the raw ID here.

(also, as a general remark, it's easier on us to not send the patches
during the rc6 <-> rc1 phase), so if you can resend them as soon as
rc1 is out, that would be great :)

Maxime
Jernej Skrabec Jan. 27, 2020, 7:05 p.m. UTC | #2
Dne ponedeljek, 27. januar 2020 ob 15:59:31 CET je Maxime Ripard napisal(a):
> Hi,
> 
> On Sat, Jan 25, 2020 at 12:03:51PM +0100, Jernej Skrabec wrote:
> > A64 contains MBUS, which is the bus used by DMA devices to access
> > system memory.
> > 
> > MBUS controller is responsible for arbitration between channels based
> > on set priority and can do some other things as well, like report
> > bandwidth used. It also maps RAM region to different address than CPU.
> > 
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > ---
> > 
> >  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index
> > 862b47dc9dc9..d225ea1f3b87 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > @@ -1061,6 +1061,14 @@ pwm: pwm@1c21400 {
> > 
> >  			status = "disabled";
> >  		
> >  		};
> > 
> > +		mbus: dram-controller@1c62000 {
> > +			compatible = "allwinner,sun50i-a64-mbus";
> > +			reg = <0x01c62000 0x1000>;
> > +			clocks = <&ccu CLK_MBUS>;
> 
> We're merging the clock header patch and the DT through two different
> trees, so you can't use it right away. You should use the raw ID here.

Ok.

> 
> (also, as a general remark, it's easier on us to not send the patches
> during the rc6 <-> rc1 phase), so if you can resend them as soon as
> rc1 is out, that would be great :)

Ok, I'll send v2 then.

Best regards,
Jernej