[v2,00/11] Move PMC clocks into Tegra PMC driver
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Message ID 1574830773-14892-1-git-send-email-skomatineni@nvidia.com
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  • Move PMC clocks into Tegra PMC driver
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Sowjanya Komatineni Nov. 27, 2019, 4:59 a.m. UTC
Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
are currently registered by Tegra clock driver using clk_regiser_mux and
clk_register_gate which performs direct Tegra PMC register access.

When Tegra PMC is in secure mode, any access from non-secure world will
not go through.

This patch series adds these Tegra PMC clocks and blink controls to Tegra
PMC driver with PMC as clock provider and removed them from Tegra clock
driver. This also adds PMC specific clock id's to use in device tree and
removed clock ids of PMC clock from Tegra clock driver.

This series also includes patch to update clock provider from tegra_car
to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.

[v2]:	Changes between v1 and v2 are
	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
	- feedback related to pmc clocks in Tegra PMC driver from v1
	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
	  by the clock driver using helper functions from Tegra PMC.

 	  Note:
	  To use helper functions from PMC driver, PMC early init need to
	  happen prior to using helper functions and these helper functions are
	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
	  clock registration which happen in clock_init prior to Tegra PMC
	  probe.
	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
	  tegra_mc_init.
	  This implementation of configuring PMC registers thru helper
	  functions in clock driver needs proper changes across PMC, Clock,
	  EMC and MC inits to have it work across all Tegra platforms.

	  Currently PLLM Override is not enabled in the bootloader so proper
	  patches for this fix will be taken care separately.

[v1]:	v1 includes patches for below fixes.
	- adding clk_out_1, clk_out_2, clk_out_3, blink controls to Tegra PMC
	  driver and removing clk-tegra-pmc.
	- updated clock provider from tegra_car to pmc in the device tree
	  tegra210-smaug.dts that uses clk_out_2.
	- Added helper functions in PMC driver for WB0 PLLM overrides and PLLE
	  IDDQ programming to use by clock driver and updated clock driver to
	  use these helper functions and removed direct PMC access from clock
	  driver and all pmc base address references in clock driver.


Sowjanya Komatineni (11):
  dt-bindings: soc: tegra-pmc: Add Tegra PMC clock ids
  soc: tegra: Add Tegra PMC clock registrations into PMC driver
  dt-bindings: soc: tegra-pmc: Add id for Tegra PMC blink control
  soc: pmc: Add blink output clock registration to Tegra PMC
  clk: tegra: Remove tegra_pmc_clk_init along with clk ids
  dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings
  arm: tegra: Add clock-cells property to Tegra PMC
  arm64: tegra: Add clock-cells property to Tegra pmc
  dt-bindings: Add Tegra PMC clock configuration bindings
  arm64: tegra: smaug: Change clk_out_2 provider from tegra_car to pmc
  ASoC: nau8825: change Tegra clk_out_2 provider from tegra_car to pmc

 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      |  45 ++-
 .../devicetree/bindings/sound/nau8825.txt          |   2 +-
 arch/arm/boot/dts/tegra114.dtsi                    |   4 +-
 arch/arm/boot/dts/tegra124.dtsi                    |   4 +-
 arch/arm/boot/dts/tegra20.dtsi                     |   4 +-
 arch/arm/boot/dts/tegra30.dtsi                     |   4 +-
 arch/arm64/boot/dts/nvidia/tegra132.dtsi           |   4 +-
 arch/arm64/boot/dts/nvidia/tegra186.dtsi           |   2 +
 arch/arm64/boot/dts/nvidia/tegra194.dtsi           |   2 +
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts      |   2 +-
 arch/arm64/boot/dts/nvidia/tegra210.dtsi           |   2 +
 drivers/clk/tegra/Makefile                         |   1 -
 drivers/clk/tegra/clk-id.h                         |   7 -
 drivers/clk/tegra/clk-tegra-pmc.c                  | 122 -------
 drivers/clk/tegra/clk-tegra114.c                   |  11 -
 drivers/clk/tegra/clk-tegra124.c                   |  27 +-
 drivers/clk/tegra/clk-tegra20.c                    |   4 -
 drivers/clk/tegra/clk-tegra210.c                   |  11 -
 drivers/clk/tegra/clk-tegra30.c                    |  12 -
 drivers/clk/tegra/clk.h                            |   1 -
 drivers/soc/tegra/pmc.c                            | 379 +++++++++++++++++++++
 include/dt-bindings/clock/tegra114-car.h           |  14 +-
 include/dt-bindings/clock/tegra124-car-common.h    |  14 +-
 include/dt-bindings/clock/tegra20-car.h            |   2 +-
 include/dt-bindings/clock/tegra210-car.h           |  14 +-
 include/dt-bindings/clock/tegra30-car.h            |  14 +-
 include/dt-bindings/soc/tegra-pmc.h                |  19 ++
 27 files changed, 501 insertions(+), 226 deletions(-)
 delete mode 100644 drivers/clk/tegra/clk-tegra-pmc.c
 create mode 100644 include/dt-bindings/soc/tegra-pmc.h

Comments

Dmitry Osipenko Nov. 27, 2019, 2:31 p.m. UTC | #1
27.11.2019 07:59, Sowjanya Komatineni пишет:
> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> are currently registered by Tegra clock driver using clk_regiser_mux and
> clk_register_gate which performs direct Tegra PMC register access.
> 
> When Tegra PMC is in secure mode, any access from non-secure world will
> not go through.
> 
> This patch series adds these Tegra PMC clocks and blink controls to Tegra
> PMC driver with PMC as clock provider and removed them from Tegra clock
> driver. This also adds PMC specific clock id's to use in device tree and
> removed clock ids of PMC clock from Tegra clock driver.
> 
> This series also includes patch to update clock provider from tegra_car
> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.
> 
> [v2]:	Changes between v1 and v2 are
> 	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
> 	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
> 	- feedback related to pmc clocks in Tegra PMC driver from v1
> 	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
> 	  by the clock driver using helper functions from Tegra PMC.
> 
>  	  Note:
> 	  To use helper functions from PMC driver, PMC early init need to
> 	  happen prior to using helper functions and these helper functions are
> 	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
> 	  clock registration which happen in clock_init prior to Tegra PMC
> 	  probe.
> 	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
> 	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
> 	  tegra_mc_init.
> 	  This implementation of configuring PMC registers thru helper
> 	  functions in clock driver needs proper changes across PMC, Clock,
> 	  EMC and MC inits to have it work across all Tegra platforms.
> 
> 	  Currently PLLM Override is not enabled in the bootloader so proper
> 	  patches for this fix will be taken care separately.

Hello Sowjanya,

Could you please clarify what do you mean by "PLLM Override not enabled
in bootloader"?

There is T124 Nyan Big Chromebook which is supported in upstream kernel,
it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
which has the PLLM Override set by bootloader as well. It's not clear to
me whether this patch series is supposed to break these devices. If the
breakage is the case here, then I'm afraid you can't postpone supporting
the PLLM Override and a full-featured implementation is needed.

I briefly tried to test this series on T30 and this time it doesn't hang
on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
chip uses the Blink clock source and the clock should be enabled by the
MMC core because this is how DT part looks like:

brcm_wifi_pwrseq: wifi-pwrseq {
	compatible = "mmc-pwrseq-simple";
	clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
	clock-names = "ext_clock";
	reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
	post-power-on-delay-ms = <300>;
	power-off-delay-us = <300>;
};

BTW, I  tried this series on a T20 device which also uses the Blink
clock for WiFi card and it works. So looks like this patchset has some
problem in regards to the T30 PMC clocks implementation.

[snip]
Sowjanya Komatineni Nov. 27, 2019, 5:02 p.m. UTC | #2
On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>> are currently registered by Tegra clock driver using clk_regiser_mux and
>> clk_register_gate which performs direct Tegra PMC register access.
>>
>> When Tegra PMC is in secure mode, any access from non-secure world will
>> not go through.
>>
>> This patch series adds these Tegra PMC clocks and blink controls to Tegra
>> PMC driver with PMC as clock provider and removed them from Tegra clock
>> driver. This also adds PMC specific clock id's to use in device tree and
>> removed clock ids of PMC clock from Tegra clock driver.
>>
>> This series also includes patch to update clock provider from tegra_car
>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.
>>
>> [v2]:	Changes between v1 and v2 are
>> 	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>> 	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>> 	- feedback related to pmc clocks in Tegra PMC driver from v1
>> 	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
>> 	  by the clock driver using helper functions from Tegra PMC.
>>
>>   	  Note:
>> 	  To use helper functions from PMC driver, PMC early init need to
>> 	  happen prior to using helper functions and these helper functions are
>> 	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
>> 	  clock registration which happen in clock_init prior to Tegra PMC
>> 	  probe.
>> 	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>> 	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
>> 	  tegra_mc_init.
>> 	  This implementation of configuring PMC registers thru helper
>> 	  functions in clock driver needs proper changes across PMC, Clock,
>> 	  EMC and MC inits to have it work across all Tegra platforms.
>>
>> 	  Currently PLLM Override is not enabled in the bootloader so proper
>> 	  patches for this fix will be taken care separately.
> Hello Sowjanya,
>
> Could you please clarify what do you mean by "PLLM Override not enabled
> in bootloader"?
>
> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
> which has the PLLM Override set by bootloader as well. It's not clear to
> me whether this patch series is supposed to break these devices. If the
> breakage is the case here, then I'm afraid you can't postpone supporting
> the PLLM Override and a full-featured implementation is needed.

Hi Dmitry,

Secure boot currently is enabled only on Tegra210 and Tegra210 
bootloader doesn't enable PLLM override.

So PLLM override/PLLE IDDQ being in clock driver currently will not 
break on any of existing Tegra platforms.

>
> I briefly tried to test this series on T30 and this time it doesn't hang
> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
> chip uses the Blink clock source and the clock should be enabled by the
> MMC core because this is how DT part looks like:
>
> brcm_wifi_pwrseq: wifi-pwrseq {
> 	compatible = "mmc-pwrseq-simple";
> 	clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
> 	clock-names = "ext_clock";
> 	reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
> 	post-power-on-delay-ms = <300>;
> 	power-off-delay-us = <300>;
> };
>
> BTW, I  tried this series on a T20 device which also uses the Blink
> clock for WiFi card and it works. So looks like this patchset has some
> problem in regards to the T30 PMC clocks implementation.
>
> [snip]

Blink init state is set to true for both Tegra20 and Tegra30 and all go 
through the same blink programming sequence.

Will try to add more debug messages to dump registers and will test 
blink through device tree on T30 and will get back...
Sowjanya Komatineni Nov. 27, 2019, 9:38 p.m. UTC | #3
On 11/27/19 9:02 AM, Sowjanya Komatineni wrote:
>
> On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>> are currently registered by Tegra clock driver using clk_regiser_mux 
>>> and
>>> clk_register_gate which performs direct Tegra PMC register access.
>>>
>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>> not go through.
>>>
>>> This patch series adds these Tegra PMC clocks and blink controls to 
>>> Tegra
>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>> driver. This also adds PMC specific clock id's to use in device tree 
>>> and
>>> removed clock ids of PMC clock from Tegra clock driver.
>>>
>>> This series also includes patch to update clock provider from tegra_car
>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 
>>> from PMC.
>>>
>>> [v2]:    Changes between v1 and v2 are
>>>     - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>>       blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>>     - feedback related to pmc clocks in Tegra PMC driver from v1
>>>     - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC 
>>> programming
>>>       by the clock driver using helper functions from Tegra PMC.
>>>
>>>         Note:
>>>       To use helper functions from PMC driver, PMC early init need to
>>>       happen prior to using helper functions and these helper 
>>> functions are
>>>       for PLLM Override and PLLE IDDQ programming in PMC during 
>>> PLLM/PLLE
>>>       clock registration which happen in clock_init prior to Tegra PMC
>>>       probe.
>>>       Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>>       impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>>       tegra_mc_init.
>>>       This implementation of configuring PMC registers thru helper
>>>       functions in clock driver needs proper changes across PMC, Clock,
>>>       EMC and MC inits to have it work across all Tegra platforms.
>>>
>>>       Currently PLLM Override is not enabled in the bootloader so 
>>> proper
>>>       patches for this fix will be taken care separately.
>> Hello Sowjanya,
>>
>> Could you please clarify what do you mean by "PLLM Override not enabled
>> in bootloader"?
>>
>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>> which has the PLLM Override set by bootloader as well. It's not clear to
>> me whether this patch series is supposed to break these devices. If the
>> breakage is the case here, then I'm afraid you can't postpone supporting
>> the PLLM Override and a full-featured implementation is needed.
>
> Hi Dmitry,
>
> Secure boot currently is enabled only on Tegra210 and Tegra210 
> bootloader doesn't enable PLLM override.
>
> So PLLM override/PLLE IDDQ being in clock driver currently will not 
> break on any of existing Tegra platforms.
>
>>
>> I briefly tried to test this series on T30 and this time it doesn't hang
>> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
>> chip uses the Blink clock source and the clock should be enabled by the
>> MMC core because this is how DT part looks like:
>>
>> brcm_wifi_pwrseq: wifi-pwrseq {
>>     compatible = "mmc-pwrseq-simple";
>>     clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
>>     clock-names = "ext_clock";
>>     reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
>>     post-power-on-delay-ms = <300>;
>>     power-off-delay-us = <300>;
>> };
>>
>> BTW, I  tried this series on a T20 device which also uses the Blink
>> clock for WiFi card and it works. So looks like this patchset has some
>> problem in regards to the T30 PMC clocks implementation.
>>
>> [snip]
>
> Blink init state is set to true for both Tegra20 and Tegra30 and all 
> go through the same blink programming sequence.
>
> Will try to add more debug messages to dump registers and will test 
> blink through device tree on T30 and will get back...
>
>
define value for BLINK uses BIT macro instead of just position. Will fix 
this in v3.
Thierry Reding Nov. 28, 2019, 12:26 p.m. UTC | #4
On Wed, Nov 27, 2019 at 05:31:34PM +0300, Dmitry Osipenko wrote:
> 27.11.2019 07:59, Sowjanya Komatineni пишет:
> > Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
> > are currently registered by Tegra clock driver using clk_regiser_mux and
> > clk_register_gate which performs direct Tegra PMC register access.
> > 
> > When Tegra PMC is in secure mode, any access from non-secure world will
> > not go through.
> > 
> > This patch series adds these Tegra PMC clocks and blink controls to Tegra
> > PMC driver with PMC as clock provider and removed them from Tegra clock
> > driver. This also adds PMC specific clock id's to use in device tree and
> > removed clock ids of PMC clock from Tegra clock driver.
> > 
> > This series also includes patch to update clock provider from tegra_car
> > to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.
> > 
> > [v2]:	Changes between v1 and v2 are
> > 	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
> > 	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
> > 	- feedback related to pmc clocks in Tegra PMC driver from v1
> > 	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
> > 	  by the clock driver using helper functions from Tegra PMC.
> > 
> >  	  Note:
> > 	  To use helper functions from PMC driver, PMC early init need to
> > 	  happen prior to using helper functions and these helper functions are
> > 	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
> > 	  clock registration which happen in clock_init prior to Tegra PMC
> > 	  probe.
> > 	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
> > 	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
> > 	  tegra_mc_init.
> > 	  This implementation of configuring PMC registers thru helper
> > 	  functions in clock driver needs proper changes across PMC, Clock,
> > 	  EMC and MC inits to have it work across all Tegra platforms.
> > 
> > 	  Currently PLLM Override is not enabled in the bootloader so proper
> > 	  patches for this fix will be taken care separately.
> 
> Hello Sowjanya,
> 
> Could you please clarify what do you mean by "PLLM Override not enabled
> in bootloader"?
> 
> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
> which has the PLLM Override set by bootloader as well. It's not clear to
> me whether this patch series is supposed to break these devices. If the
> breakage is the case here, then I'm afraid you can't postpone supporting
> the PLLM Override and a full-featured implementation is needed.

For some more background on why we chose to take this shortcut for now:
Sowjanya was looking at the full-featured implementation and that ended
up being a can of worms. The problem is that there are various inter-
dependencies between the PLLM override and the MC/EMC clocks.

Unfortunately we depend a lot on the explicit ordering of driver probe,
especially during early boot, so this started to get very complicated,
very quickly.

The bottom line was basically that we would need to move a whole bunch
of clocks to register at a very late point in time and support deferred
probe throughout in order to make it all work together nicely. Sowjanya
had a crack at that, and while the system ended up booting, there were a
number of errors from the MC and IOMMU drivers.

At the end, we decided to take a look at that separately because, as was
mentioned earlier, the PLLM override is not used on platforms where the
PMC is locked down, so the existing PLLM override code is going to
continue to work fine on the platforms where it's currently used.

Thierry

> I briefly tried to test this series on T30 and this time it doesn't hang
> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
> chip uses the Blink clock source and the clock should be enabled by the
> MMC core because this is how DT part looks like:
> 
> brcm_wifi_pwrseq: wifi-pwrseq {
> 	compatible = "mmc-pwrseq-simple";
> 	clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
> 	clock-names = "ext_clock";
> 	reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
> 	post-power-on-delay-ms = <300>;
> 	power-off-delay-us = <300>;
> };
> 
> BTW, I  tried this series on a T20 device which also uses the Blink
> clock for WiFi card and it works. So looks like this patchset has some
> problem in regards to the T30 PMC clocks implementation.
> 
> [snip]
Dmitry Osipenko Nov. 28, 2019, 1:06 p.m. UTC | #5
28.11.2019 00:38, Sowjanya Komatineni пишет:
> 
> On 11/27/19 9:02 AM, Sowjanya Komatineni wrote:
>>
>> On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>>> are currently registered by Tegra clock driver using clk_regiser_mux
>>>> and
>>>> clk_register_gate which performs direct Tegra PMC register access.
>>>>
>>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>>> not go through.
>>>>
>>>> This patch series adds these Tegra PMC clocks and blink controls to
>>>> Tegra
>>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>>> driver. This also adds PMC specific clock id's to use in device tree
>>>> and
>>>> removed clock ids of PMC clock from Tegra clock driver.
>>>>
>>>> This series also includes patch to update clock provider from tegra_car
>>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2
>>>> from PMC.
>>>>
>>>> [v2]:    Changes between v1 and v2 are
>>>>     - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>>>       blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>>>     - feedback related to pmc clocks in Tegra PMC driver from v1
>>>>     - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC
>>>> programming
>>>>       by the clock driver using helper functions from Tegra PMC.
>>>>
>>>>         Note:
>>>>       To use helper functions from PMC driver, PMC early init need to
>>>>       happen prior to using helper functions and these helper
>>>> functions are
>>>>       for PLLM Override and PLLE IDDQ programming in PMC during
>>>> PLLM/PLLE
>>>>       clock registration which happen in clock_init prior to Tegra PMC
>>>>       probe.
>>>>       Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>>>       impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>>>       tegra_mc_init.
>>>>       This implementation of configuring PMC registers thru helper
>>>>       functions in clock driver needs proper changes across PMC, Clock,
>>>>       EMC and MC inits to have it work across all Tegra platforms.
>>>>
>>>>       Currently PLLM Override is not enabled in the bootloader so
>>>> proper
>>>>       patches for this fix will be taken care separately.
>>> Hello Sowjanya,
>>>
>>> Could you please clarify what do you mean by "PLLM Override not enabled
>>> in bootloader"?
>>>
>>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>>> which has the PLLM Override set by bootloader as well. It's not clear to
>>> me whether this patch series is supposed to break these devices. If the
>>> breakage is the case here, then I'm afraid you can't postpone supporting
>>> the PLLM Override and a full-featured implementation is needed.
>>
>> Hi Dmitry,
>>
>> Secure boot currently is enabled only on Tegra210 and Tegra210
>> bootloader doesn't enable PLLM override.
>>
>> So PLLM override/PLLE IDDQ being in clock driver currently will not
>> break on any of existing Tegra platforms.
>>
>>>
>>> I briefly tried to test this series on T30 and this time it doesn't hang
>>> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
>>> chip uses the Blink clock source and the clock should be enabled by the
>>> MMC core because this is how DT part looks like:
>>>
>>> brcm_wifi_pwrseq: wifi-pwrseq {
>>>     compatible = "mmc-pwrseq-simple";
>>>     clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
>>>     clock-names = "ext_clock";
>>>     reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
>>>     post-power-on-delay-ms = <300>;
>>>     power-off-delay-us = <300>;
>>> };
>>>
>>> BTW, I  tried this series on a T20 device which also uses the Blink
>>> clock for WiFi card and it works. So looks like this patchset has some
>>> problem in regards to the T30 PMC clocks implementation.
>>>
>>> [snip]
>>
>> Blink init state is set to true for both Tegra20 and Tegra30 and all
>> go through the same blink programming sequence.
>>
>> Will try to add more debug messages to dump registers and will test
>> blink through device tree on T30 and will get back...
>>
>>
> define value for BLINK uses BIT macro instead of just position. Will fix
> this in v3.

Thanks, will try v3 once it will be ready.

I took a look through the T20 board's schematics and seems it doesn't
use the Blink clock for the WiFi, instead it uses 32k source directly
from PMU. While T30 board schematics tells that  32k comes out from the
Tegra chip.

BTW, I'm curious what's the reason for having Blink clock always-ON on
T20/30, any insights? Looks like it's just some relic from old clk
driver and it should be safe to drop the always-ON.
Dmitry Osipenko Nov. 28, 2019, 1:10 p.m. UTC | #6
28.11.2019 15:26, Thierry Reding пишет:
> On Wed, Nov 27, 2019 at 05:31:34PM +0300, Dmitry Osipenko wrote:
>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>> are currently registered by Tegra clock driver using clk_regiser_mux and
>>> clk_register_gate which performs direct Tegra PMC register access.
>>>
>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>> not go through.
>>>
>>> This patch series adds these Tegra PMC clocks and blink controls to Tegra
>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>> driver. This also adds PMC specific clock id's to use in device tree and
>>> removed clock ids of PMC clock from Tegra clock driver.
>>>
>>> This series also includes patch to update clock provider from tegra_car
>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2 from PMC.
>>>
>>> [v2]:	Changes between v1 and v2 are
>>> 	- v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>> 	  blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>> 	- feedback related to pmc clocks in Tegra PMC driver from v1
>>> 	- Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC programming
>>> 	  by the clock driver using helper functions from Tegra PMC.
>>>
>>>  	  Note:
>>> 	  To use helper functions from PMC driver, PMC early init need to
>>> 	  happen prior to using helper functions and these helper functions are
>>> 	  for PLLM Override and PLLE IDDQ programming in PMC during PLLM/PLLE
>>> 	  clock registration which happen in clock_init prior to Tegra PMC
>>> 	  probe.
>>> 	  Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>> 	  impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>> 	  tegra_mc_init.
>>> 	  This implementation of configuring PMC registers thru helper
>>> 	  functions in clock driver needs proper changes across PMC, Clock,
>>> 	  EMC and MC inits to have it work across all Tegra platforms.
>>>
>>> 	  Currently PLLM Override is not enabled in the bootloader so proper
>>> 	  patches for this fix will be taken care separately.
>>
>> Hello Sowjanya,
>>
>> Could you please clarify what do you mean by "PLLM Override not enabled
>> in bootloader"?
>>
>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>> which has the PLLM Override set by bootloader as well. It's not clear to
>> me whether this patch series is supposed to break these devices. If the
>> breakage is the case here, then I'm afraid you can't postpone supporting
>> the PLLM Override and a full-featured implementation is needed.
> 
> For some more background on why we chose to take this shortcut for now:
> Sowjanya was looking at the full-featured implementation and that ended
> up being a can of worms. The problem is that there are various inter-
> dependencies between the PLLM override and the MC/EMC clocks.
> 
> Unfortunately we depend a lot on the explicit ordering of driver probe,
> especially during early boot, so this started to get very complicated,
> very quickly.
> 
> The bottom line was basically that we would need to move a whole bunch
> of clocks to register at a very late point in time and support deferred
> probe throughout in order to make it all work together nicely. Sowjanya
> had a crack at that, and while the system ended up booting, there were a
> number of errors from the MC and IOMMU drivers.
> 
> At the end, we decided to take a look at that separately because, as was
> mentioned earlier, the PLLM override is not used on platforms where the
> PMC is locked down, so the existing PLLM override code is going to
> continue to work fine on the platforms where it's currently used.
> 
> Thierry

Thank you and Sowjanya for the clarification.

[snip]
Dmitry Osipenko Dec. 2, 2019, 5:09 p.m. UTC | #7
28.11.2019 16:06, Dmitry Osipenko пишет:
> 28.11.2019 00:38, Sowjanya Komatineni пишет:
>>
>> On 11/27/19 9:02 AM, Sowjanya Komatineni wrote:
>>>
>>> On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>>>> are currently registered by Tegra clock driver using clk_regiser_mux
>>>>> and
>>>>> clk_register_gate which performs direct Tegra PMC register access.
>>>>>
>>>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>>>> not go through.
>>>>>
>>>>> This patch series adds these Tegra PMC clocks and blink controls to
>>>>> Tegra
>>>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>>>> driver. This also adds PMC specific clock id's to use in device tree
>>>>> and
>>>>> removed clock ids of PMC clock from Tegra clock driver.
>>>>>
>>>>> This series also includes patch to update clock provider from tegra_car
>>>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2
>>>>> from PMC.
>>>>>
>>>>> [v2]:    Changes between v1 and v2 are
>>>>>     - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>>>>       blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>>>>     - feedback related to pmc clocks in Tegra PMC driver from v1
>>>>>     - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC
>>>>> programming
>>>>>       by the clock driver using helper functions from Tegra PMC.
>>>>>
>>>>>         Note:
>>>>>       To use helper functions from PMC driver, PMC early init need to
>>>>>       happen prior to using helper functions and these helper
>>>>> functions are
>>>>>       for PLLM Override and PLLE IDDQ programming in PMC during
>>>>> PLLM/PLLE
>>>>>       clock registration which happen in clock_init prior to Tegra PMC
>>>>>       probe.
>>>>>       Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>>>>       impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>>>>       tegra_mc_init.
>>>>>       This implementation of configuring PMC registers thru helper
>>>>>       functions in clock driver needs proper changes across PMC, Clock,
>>>>>       EMC and MC inits to have it work across all Tegra platforms.
>>>>>
>>>>>       Currently PLLM Override is not enabled in the bootloader so
>>>>> proper
>>>>>       patches for this fix will be taken care separately.
>>>> Hello Sowjanya,
>>>>
>>>> Could you please clarify what do you mean by "PLLM Override not enabled
>>>> in bootloader"?
>>>>
>>>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>>>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>>>> which has the PLLM Override set by bootloader as well. It's not clear to
>>>> me whether this patch series is supposed to break these devices. If the
>>>> breakage is the case here, then I'm afraid you can't postpone supporting
>>>> the PLLM Override and a full-featured implementation is needed.
>>>
>>> Hi Dmitry,
>>>
>>> Secure boot currently is enabled only on Tegra210 and Tegra210
>>> bootloader doesn't enable PLLM override.
>>>
>>> So PLLM override/PLLE IDDQ being in clock driver currently will not
>>> break on any of existing Tegra platforms.
>>>
>>>>
>>>> I briefly tried to test this series on T30 and this time it doesn't hang
>>>> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
>>>> chip uses the Blink clock source and the clock should be enabled by the
>>>> MMC core because this is how DT part looks like:
>>>>
>>>> brcm_wifi_pwrseq: wifi-pwrseq {
>>>>     compatible = "mmc-pwrseq-simple";
>>>>     clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
>>>>     clock-names = "ext_clock";
>>>>     reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
>>>>     post-power-on-delay-ms = <300>;
>>>>     power-off-delay-us = <300>;
>>>> };
>>>>
>>>> BTW, I  tried this series on a T20 device which also uses the Blink
>>>> clock for WiFi card and it works. So looks like this patchset has some
>>>> problem in regards to the T30 PMC clocks implementation.
>>>>
>>>> [snip]
>>>
>>> Blink init state is set to true for both Tegra20 and Tegra30 and all
>>> go through the same blink programming sequence.
>>>
>>> Will try to add more debug messages to dump registers and will test
>>> blink through device tree on T30 and will get back...
>>>
>>>
>> define value for BLINK uses BIT macro instead of just position. Will fix
>> this in v3.
> 
> Thanks, will try v3 once it will be ready.
> 
> I took a look through the T20 board's schematics and seems it doesn't
> use the Blink clock for the WiFi, instead it uses 32k source directly
> from PMU. While T30 board schematics tells that  32k comes out from the
> Tegra chip.

That was wrong, both T20 and T30 are identical in regards to the clk32k
wiring. I'm not sure what's difference between T20 and T30 that made
WiFi card not to work without the blink clock on T30, maybe it's a WiFi
chip difference.

> BTW, I'm curious what's the reason for having Blink clock always-ON on
> T20/30, any insights? Looks like it's just some relic from old clk
> driver and it should be safe to drop the always-ON.
>
Sowjanya Komatineni Dec. 2, 2019, 6:47 p.m. UTC | #8
On 11/28/19 5:06 AM, Dmitry Osipenko wrote:
> 28.11.2019 00:38, Sowjanya Komatineni пишет:
>> On 11/27/19 9:02 AM, Sowjanya Komatineni wrote:
>>> On 11/27/19 6:31 AM, Dmitry Osipenko wrote:
>>>> 27.11.2019 07:59, Sowjanya Komatineni пишет:
>>>>> Tegra PMC has clk_out_1, clk_out_2, clk_out_3 and blink controls which
>>>>> are currently registered by Tegra clock driver using clk_regiser_mux
>>>>> and
>>>>> clk_register_gate which performs direct Tegra PMC register access.
>>>>>
>>>>> When Tegra PMC is in secure mode, any access from non-secure world will
>>>>> not go through.
>>>>>
>>>>> This patch series adds these Tegra PMC clocks and blink controls to
>>>>> Tegra
>>>>> PMC driver with PMC as clock provider and removed them from Tegra clock
>>>>> driver. This also adds PMC specific clock id's to use in device tree
>>>>> and
>>>>> removed clock ids of PMC clock from Tegra clock driver.
>>>>>
>>>>> This series also includes patch to update clock provider from tegra_car
>>>>> to pmc in the device tree tegra210-smaug.dts that uses clk_out_2
>>>>> from PMC.
>>>>>
>>>>> [v2]:    Changes between v1 and v2 are
>>>>>      - v2 includes patches for adding clk_out_1, clk_out_2, clk_out_3,
>>>>>        blink controls to Tegra PMC driver and removing clk-tegra-pmc.
>>>>>      - feedback related to pmc clocks in Tegra PMC driver from v1
>>>>>      - Removed patches for WB0 PLLM overrides and PLLE IDDQ PMC
>>>>> programming
>>>>>        by the clock driver using helper functions from Tegra PMC.
>>>>>
>>>>>          Note:
>>>>>        To use helper functions from PMC driver, PMC early init need to
>>>>>        happen prior to using helper functions and these helper
>>>>> functions are
>>>>>        for PLLM Override and PLLE IDDQ programming in PMC during
>>>>> PLLM/PLLE
>>>>>        clock registration which happen in clock_init prior to Tegra PMC
>>>>>        probe.
>>>>>        Moving PLLM/PLLE clocks registration to happen after Tegra PMC
>>>>>        impacts other clocks EMC, MC and corresponding tegra_emc_init and
>>>>>        tegra_mc_init.
>>>>>        This implementation of configuring PMC registers thru helper
>>>>>        functions in clock driver needs proper changes across PMC, Clock,
>>>>>        EMC and MC inits to have it work across all Tegra platforms.
>>>>>
>>>>>        Currently PLLM Override is not enabled in the bootloader so
>>>>> proper
>>>>>        patches for this fix will be taken care separately.
>>>> Hello Sowjanya,
>>>>
>>>> Could you please clarify what do you mean by "PLLM Override not enabled
>>>> in bootloader"?
>>>>
>>>> There is T124 Nyan Big Chromebook which is supported in upstream kernel,
>>>> it has PLLM Override set by bootloader. I also have T30 Nexus 7 tablet
>>>> which has the PLLM Override set by bootloader as well. It's not clear to
>>>> me whether this patch series is supposed to break these devices. If the
>>>> breakage is the case here, then I'm afraid you can't postpone supporting
>>>> the PLLM Override and a full-featured implementation is needed.
>>> Hi Dmitry,
>>>
>>> Secure boot currently is enabled only on Tegra210 and Tegra210
>>> bootloader doesn't enable PLLM override.
>>>
>>> So PLLM override/PLLE IDDQ being in clock driver currently will not
>>> break on any of existing Tegra platforms.
>>>
>>>> I briefly tried to test this series on T30 and this time it doesn't hang
>>>> on boot, but somehow WiFi MMC card detection is broken. AFAIK, the WiFi
>>>> chip uses the Blink clock source and the clock should be enabled by the
>>>> MMC core because this is how DT part looks like:
>>>>
>>>> brcm_wifi_pwrseq: wifi-pwrseq {
>>>>      compatible = "mmc-pwrseq-simple";
>>>>      clocks = <&pmc TEGRA_PMC_CLK_BLINK>;
>>>>      clock-names = "ext_clock";
>>>>      reset-gpios =  <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
>>>>      post-power-on-delay-ms = <300>;
>>>>      power-off-delay-us = <300>;
>>>> };
>>>>
>>>> BTW, I  tried this series on a T20 device which also uses the Blink
>>>> clock for WiFi card and it works. So looks like this patchset has some
>>>> problem in regards to the T30 PMC clocks implementation.
>>>>
>>>> [snip]
>>> Blink init state is set to true for both Tegra20 and Tegra30 and all
>>> go through the same blink programming sequence.
>>>
>>> Will try to add more debug messages to dump registers and will test
>>> blink through device tree on T30 and will get back...
>>>
>>>
>> define value for BLINK uses BIT macro instead of just position. Will fix
>> this in v3.
> Thanks, will try v3 once it will be ready.
>
> I took a look through the T20 board's schematics and seems it doesn't
> use the Blink clock for the WiFi, instead it uses 32k source directly
> from PMU. While T30 board schematics tells that  32k comes out from the
> Tegra chip.
>
> BTW, I'm curious what's the reason for having Blink clock always-ON on
> T20/30, any insights? Looks like it's just some relic from old clk
> driver and it should be safe to drop the always-ON.

T30 cardhu uses 32K from Tegra to WIFI but its only needed to be on 
during WIFI power up sequence and not required to be on during boot.

I had it enabled as existing clock driver enables it default and dont 
want to break things if it was left ON intentionally.

Peter/Thierry, Any reason 32K from Blink is enabled to be ON during 
clock init for T20/T30 in clock-tegra-pmc driver?

Based on the design T30 uses this for WIFI and WIFI driver should be 
handling this clock enable/disable during power up/down sequence,

so we don't have to enable it default during boot right?