| Message ID | 20191102112316.20715-1-tudor.ambarus@microchip.com |
|---|---|
| Headers | show |
| Series | mtd: spi-nor: Quad Enable and (un)lock methods | expand |
On 11/02/2019 01:23 PM, Tudor Ambarus - M18064 wrote: > From: Tudor Ambarus <tudor.ambarus@microchip.com> > > Tested on s25fl116k and w25q128jv-q. > > Fixed the clearing of QE bit on (un)lock() operations. Reworked the > Quad Enable methods and the disabling of the block write protection > at power-up. > > v4: > - Use dev_dbg insted of dev_err for low level info > - replace "&nor->bouncebuf[0]" with "nor->bouncebuf" and "&sr_cr[0]" with > "sr_cr". Update across all patches. > > v3: split patches, update retlen handling in sst_write. > > v2: > - Introduce spi_nor_write_16bit_cr_and_check() as per Vignesh's suggestion. The > Configuration Register contains bits that can be updated in future: FREEZE, > CMP. Provide a generic method that allows updating all bits of the > Configuration Register. > - Fix SNOR_F_NO_READ_CR case in > "mtd: spi-nor: Rework the disabling of block write protection". When the flash > doesn't support the CR Read command, we make an assumption about the value of > the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then > spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be sure > the QE bit has value one, because of the previous call to spi_nor_quad_enable(). > - Fix if statement in spi_nor_write_sr_and_check(): > if (nor->flags & SNOR_F_HAS_16BIT_SR) > - Fix documentation warnings. > - New patch: "mtd: spi-nor: Check all the bits written, not just the BP ones". > - Drop Global Unlock patches, will send them in a different patch set. > > The patch set can be tested using mtd-utils: > 1/ do a read-erase-write-read-back test immediately after boot, to check > the spi_nor_unlock_all() method. The focus is on the erase/write > methods, we want to see if the flash is unlocked at power-up. > mtd_debug read /dev/mtd-yours offset size read-file > hexdump read-file > mtd_debug erase /dev/mtd-yours offset size > dd if=/dev/urandom of=write-file bs=please-choose count=please-choose > mtd_debug write /dev/mtd-yours offset write-file-size write-file > mtd_debug read /dev/mtd-yours offset write-file-size read-file > sha1sum read-file write-file > 2/ lock flash then try to erase/write it, to see if the lock works > flash_lock /dev/mtd-yours offset block-count > Do the read-erase-write-read-back test from 1/. The contents of > flash should not change in the erase and write steps. > 3/ unlock flash and do the read-erase-write-read-back from 1/. The value of the > QEE should not change and you should be able to erase and write the flash. > Test 1/ should be successful. > > Tudor Ambarus (20): > mtd: spi-nor: Use dev_dbg insted of dev_err for low level info > mtd: spi-nor: Print debug info inside Reg Ops methods > mtd: spi-nor: Check for errors after each Register Operation > mtd: spi-nor: Rename label as it is no longer generic > mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() > mtd: spi-nor: Move the WE and wait calls inside Write SR methods > mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr() > mtd: spi-nor: Describe all the Reg Ops > mtd: spi-nor: Drop spansion_quad_enable() > mtd: spi-nor: Fix errno on Quad Enable methods > mtd: spi-nor: Check all the bits written, not just the BP ones > mtd: spi-nor: Print debug message when the read back test fails > mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() > mtd: spi-nor: Extend the QE Read Back test to the entire SR byte > mtd: spi-nor: Extend the QE Read Back test to both SR1 and SR2 > mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 > mtd: spi-nor: Merge spansion Quad Enable methods > mtd: spi-nor: Rename macronix_quad_enable to > spi_nor_sr1_bit6_quad_enable > mtd: spi-nor: Prepend "spi_nor_" to "sr2_bit7_quad_enable" > mtd: spi-nor: Rework the disabling of block write protection > > drivers/mtd/spi-nor/spi-nor.c | 952 +++++++++++++++++++++++++----------------- > include/linux/mtd/spi-nor.h | 12 +- > 2 files changed, 583 insertions(+), 381 deletions(-) > Updated 1/20 to use dev_err() when the SR/FSR report program or erase fails, or attempts of modifying a protected sector. Patches 1-12 applied to spi-nor/next. Thanks.
From: Tudor Ambarus <tudor.ambarus@microchip.com> Tested on s25fl116k and w25q128jv-q. Fixed the clearing of QE bit on (un)lock() operations. Reworked the Quad Enable methods and the disabling of the block write protection at power-up. v4: - Use dev_dbg insted of dev_err for low level info - replace "&nor->bouncebuf[0]" with "nor->bouncebuf" and "&sr_cr[0]" with "sr_cr". Update across all patches. v3: split patches, update retlen handling in sst_write. v2: - Introduce spi_nor_write_16bit_cr_and_check() as per Vignesh's suggestion. The Configuration Register contains bits that can be updated in future: FREEZE, CMP. Provide a generic method that allows updating all bits of the Configuration Register. - Fix SNOR_F_NO_READ_CR case in "mtd: spi-nor: Rework the disabling of block write protection". When the flash doesn't support the CR Read command, we make an assumption about the value of the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be sure the QE bit has value one, because of the previous call to spi_nor_quad_enable(). - Fix if statement in spi_nor_write_sr_and_check(): if (nor->flags & SNOR_F_HAS_16BIT_SR) - Fix documentation warnings. - New patch: "mtd: spi-nor: Check all the bits written, not just the BP ones". - Drop Global Unlock patches, will send them in a different patch set. The patch set can be tested using mtd-utils: 1/ do a read-erase-write-read-back test immediately after boot, to check the spi_nor_unlock_all() method. The focus is on the erase/write methods, we want to see if the flash is unlocked at power-up. mtd_debug read /dev/mtd-yours offset size read-file hexdump read-file mtd_debug erase /dev/mtd-yours offset size dd if=/dev/urandom of=write-file bs=please-choose count=please-choose mtd_debug write /dev/mtd-yours offset write-file-size write-file mtd_debug read /dev/mtd-yours offset write-file-size read-file sha1sum read-file write-file 2/ lock flash then try to erase/write it, to see if the lock works flash_lock /dev/mtd-yours offset block-count Do the read-erase-write-read-back test from 1/. The contents of flash should not change in the erase and write steps. 3/ unlock flash and do the read-erase-write-read-back from 1/. The value of the QEE should not change and you should be able to erase and write the flash. Test 1/ should be successful. Tudor Ambarus (20): mtd: spi-nor: Use dev_dbg insted of dev_err for low level info mtd: spi-nor: Print debug info inside Reg Ops methods mtd: spi-nor: Check for errors after each Register Operation mtd: spi-nor: Rename label as it is no longer generic mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() mtd: spi-nor: Move the WE and wait calls inside Write SR methods mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr() mtd: spi-nor: Describe all the Reg Ops mtd: spi-nor: Drop spansion_quad_enable() mtd: spi-nor: Fix errno on Quad Enable methods mtd: spi-nor: Check all the bits written, not just the BP ones mtd: spi-nor: Print debug message when the read back test fails mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() mtd: spi-nor: Extend the QE Read Back test to the entire SR byte mtd: spi-nor: Extend the QE Read Back test to both SR1 and SR2 mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 mtd: spi-nor: Merge spansion Quad Enable methods mtd: spi-nor: Rename macronix_quad_enable to spi_nor_sr1_bit6_quad_enable mtd: spi-nor: Prepend "spi_nor_" to "sr2_bit7_quad_enable" mtd: spi-nor: Rework the disabling of block write protection drivers/mtd/spi-nor/spi-nor.c | 952 +++++++++++++++++++++++++----------------- include/linux/mtd/spi-nor.h | 12 +- 2 files changed, 583 insertions(+), 381 deletions(-)