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b=BG0beOxBnHKPalJ4WqCYehmR+CYr5NefHYVm9WkaTrd71CT7CmtvBtqGd7rsXqKTBNN1Pbj6uOvwSHxCADXLRVIhcTe7oDrEU3JCMkx/+PwrOB8eTWE3R7k6B/kKc2hYx3WSNblRFUKDdYfvo+EMSfLwIs7uR5/Pt3Qg/vvwhxU= Received: from MN2PR11MB4448.namprd11.prod.outlook.com (52.135.39.157) by MN2PR11MB3984.namprd11.prod.outlook.com (10.255.181.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2263.21; Tue, 17 Sep 2019 15:54:40 +0000 Received: from MN2PR11MB4448.namprd11.prod.outlook.com ([fe80::c951:b15a:e4b3:30f7]) by MN2PR11MB4448.namprd11.prod.outlook.com ([fe80::c951:b15a:e4b3:30f7%7]) with mapi id 15.20.2263.023; Tue, 17 Sep 2019 15:54:40 +0000 From: To: , , , , , Subject: [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Thread-Topic: [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Thread-Index: AQHVbXA3ZsB/BVyqVUKkLPfzQhFGCw== Date: Tue, 17 Sep 2019 15:54:40 +0000 Message-ID: <20190917155426.7432-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0302CA0007.eurprd03.prod.outlook.com (2603:10a6:800:e9::17) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 88283e5b-b36d-4061-758c-08d73b875983 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(711020)(4605104)(1401327)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020); SRVR:MN2PR11MB3984; x-ms-traffictypediagnostic: MN2PR11MB3984: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; x-forefront-prvs: 01630974C0 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(396003)(136003)(39860400002)(376002)(366004)(346002)(199004)(189003)(478600001)(2616005)(64756008)(66476007)(3846002)(6486002)(107886003)(25786009)(6512007)(50226002)(6436002)(305945005)(99286004)(14444005)(71200400001)(476003)(7416002)(486006)(256004)(66066001)(71190400001)(7736002)(102836004)(36756003)(26005)(386003)(66446008)(14454004)(66946007)(1076003)(86362001)(6506007)(186003)(6116002)(5660300002)(66556008)(110136005)(81156014)(81166006)(2501003)(8676002)(54906003)(316002)(4326008)(8936002)(2906002)(52116002)(2201001)(414714003)(473944003); DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR11MB3984; H:MN2PR11MB4448.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ofh6pe1v6FA/3NbOqQvSvo31cnWpwEKQTwRlOl1Py6WLd01OpltUENpUuE7ZiM3AYdcAdwbEnpxLVyKv3Je64uyvzCnhlET3Tz/fwSSfpTVAIxZo57YRc8ZvmxsmTmnuiSX4lgXyUhNmzEsgiMR1h0QFbf8c0Ngz4WrNpiNweGeix1L2ZicV1O+XA61beR3bXIFuw8saMm3Cc+wLClHkWJLQIx2XcQTx1YBmFv5x7wo7uwGCuzaOCln4FDxnDBYhTGePwcRAsINI5fE33uuJMNlIKN7NsTvulgu8YRoe8Wr+Bxc+HxncPV+jIfxLsXLtTxVMQ6sIQ2pbErXxoIKk/S0R1VQ6i9+R20sWKUHDnPW+xcNe9ABoqCKFnCX5GITy2tG35/AsViSe/+7AwldexDgk/+wCFoNSHlGXNz/MXUM= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 88283e5b-b36d-4061-758c-08d73b875983 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Sep 2019 15:54:40.7753 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: aIb127DlvcsxmJa8rtpr+Dlokbm/a5zYluVfjB0+ANLbP5pD2XbD8OvMhc99cHuyVBKDg0mhiwMqVj7PpcsyVcgz4lw1LrNFjpkyfA7FP0w= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3984 X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-aspeed@lists.ozlabs.org, Tudor.Ambarus@microchip.com, linux-kernel@vger.kernel.org, vz@mleia.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, computersforpeace@gmail.com, dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" From: Tudor Ambarus Patches 1 - 14 are just clean up patches for the Flash Register Operations. Patches 15 - 21 deal with the Quad Enable and the (un)lock methods. Fixed the clearing of QE bit on (un)lock() operations. Reworked the Quad Enable methods and the disabling of the block write protection at power-up. Patch 22 adds Global Block Unlock support as an optimization for unlocking the entire memory array. Patch 23 uses it in sst26vf064b. This is just compile tested, I don't have a relevant spansion-like flash memory to test the (un)lock() methods. The patch set can be tested using mtd-utils: 1/ do a read-erase-write-read-back test immediately after boot, to check the spi_nor_unlock_all() method mtd_debug read /dev/mtd-yours offset size read-file hexdump read-file mtd_debug erase /dev/mtd-yours offset size dd if=/dev/urandom of=write-file bs=please-choose count=please-choose mtd_debug write /dev/mtd-yours offset write-file-size write-file mtd_debug read /dev/mtd-yours offset write-file-size read-file sha1sum read-file write-file 2/ lock flash then try to erase/write it, to see if the lock works flash_lock /dev/mtd-yours offset block-count read-erase/write-read-back test 3/ unlock flash and do a read-erase-write-read-back to check if the QE bit was not cleared. Thanks, ta Tudor Ambarus (23): mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition mtd: spi-nor: Rename nor->params to nor->flash mtd: spi-nor: Rework read_sr() mtd: spi-nor: Rework read_fsr() mtd: spi-nor: Rework read_cr() mtd: spi-nor: Rework write_enable/disable() mtd: spi-nor: Fix retlen handling in sst_write() mtd: spi-nor: Rework write_sr() mtd: spi-nor: Rework spi_nor_read/write_sr2() mtd: spi-nor: Report error in spi_nor_xread_sr() mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() mtd: spi-nor: Drop duplicated new line mtd: spi-nor: Drop spansion_quad_enable() mtd: spi-nor: Fix errno on quad_enable methods mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() mtd: spi-nor: Rework macronix_quad_enable() mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable() mtd: spi-nor: Update sr2_bit7_quad_enable() mtd: spi-nor: Rework the disabling of block write protection mtd: spi-nor: Add Global Block Unlock support mtd: spi-nor: Unlock global block protection on sst26vf064b drivers/mtd/spi-nor/aspeed-smc.c | 23 +- drivers/mtd/spi-nor/cadence-quadspi.c | 54 +- drivers/mtd/spi-nor/hisi-sfc.c | 23 +- drivers/mtd/spi-nor/intel-spi.c | 24 +- drivers/mtd/spi-nor/mtk-quadspi.c | 25 +- drivers/mtd/spi-nor/nxp-spifi.c | 23 +- drivers/mtd/spi-nor/spi-nor.c | 1697 ++++++++++++++++++--------------- include/linux/mtd/spi-nor.h | 75 +- 8 files changed, 1050 insertions(+), 894 deletions(-)