| Message ID | 20190828172850.19871-1-vidyas@nvidia.com |
|---|---|
| Headers | show |
| Series | PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform | expand |
On Wed, Aug 28, 2019 at 10:58:47PM +0530, Vidya Sagar wrote: > Add support to configure sideband signal pins when information is present > in respective controller's device-tree node. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> > --- > V3: > * Used 'dev' instead of 'pcie->dev' > > V2: > * Addressed review comment from Andrew Murray > * Handled failure case of pinctrl_pm_select_default_state() cleanly > > drivers/pci/controller/dwc/pcie-tegra194.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index fc0dbeb31d78..77fa6f70bc96 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -1304,8 +1304,13 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) > if (ret < 0) { > dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n", > ret); > - pm_runtime_disable(dev); > - return ret; > + goto fail_pm_get_sync; > + } > + > + ret = pinctrl_pm_select_default_state(dev); > + if (ret < 0) { > + dev_err(dev, "Failed to configure sideband pins: %d\n", ret); > + goto fail_pinctrl; > } > > tegra_pcie_init_controller(pcie); > @@ -1332,7 +1337,9 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) > > fail_host_init: > tegra_pcie_deinit_controller(pcie); > +fail_pinctrl: > pm_runtime_put_sync(dev); > +fail_pm_get_sync: > pm_runtime_disable(dev); > return ret; > } > -- > 2.17.1 >
On Wed, Aug 28, 2019 at 10:58:48PM +0530, Vidya Sagar wrote: > Add support to get regulator information of 3.3V and 12V supplies of a PCIe > slot from the respective controller's device-tree node and enable those > supplies. This is required in platforms like p2972-0000 where the supplies > to x16 slot owned by C5 controller need to be enabled before attempting to > enumerate the devices. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> > --- > V3: > * Added a dev_err() print for failure case of tegra_pcie_get_slot_regulators() API > * Modified to make 100ms sleep valid only if at least one of the regulator handles exist > > V2: > * Addressed review comments from Thierry Reding and Andrew Murray > * Handled failure case of devm_regulator_get_optional() for -ENODEV cleanly > > drivers/pci/controller/dwc/pcie-tegra194.c | 83 ++++++++++++++++++++++ > 1 file changed, 83 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index 77fa6f70bc96..18453cc5e7e4 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -278,6 +278,8 @@ struct tegra_pcie_dw { > u32 aspm_l0s_enter_lat; > > struct regulator *pex_ctl_supply; > + struct regulator *slot_ctl_3v3; > + struct regulator *slot_ctl_12v; > > unsigned int phy_count; > struct phy **phys; > @@ -1047,6 +1049,73 @@ static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) > } > } > > +static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie) > +{ > + pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); > + if (IS_ERR(pcie->slot_ctl_3v3)) { > + if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) > + return PTR_ERR(pcie->slot_ctl_3v3); > + > + pcie->slot_ctl_3v3 = NULL; > + } > + > + pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); > + if (IS_ERR(pcie->slot_ctl_12v)) { > + if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) > + return PTR_ERR(pcie->slot_ctl_12v); > + > + pcie->slot_ctl_12v = NULL; > + } > + > + return 0; > +} > + > +static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie) > +{ > + int ret; > + > + if (pcie->slot_ctl_3v3) { > + ret = regulator_enable(pcie->slot_ctl_3v3); > + if (ret < 0) { > + dev_err(pcie->dev, > + "Failed to enable 3.3V slot supply: %d\n", ret); > + return ret; > + } > + } > + > + if (pcie->slot_ctl_12v) { > + ret = regulator_enable(pcie->slot_ctl_12v); > + if (ret < 0) { > + dev_err(pcie->dev, > + "Failed to enable 12V slot supply: %d\n", ret); > + goto fail_12v_enable; > + } > + } > + > + /* > + * According to PCI Express Card Electromechanical Specification > + * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) > + * should be a minimum of 100ms. > + */ > + if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) > + msleep(100); > + > + return 0; > + > +fail_12v_enable: > + if (pcie->slot_ctl_3v3) > + regulator_disable(pcie->slot_ctl_3v3); > + return ret; > +} > + > +static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie) > +{ > + if (pcie->slot_ctl_12v) > + regulator_disable(pcie->slot_ctl_12v); > + if (pcie->slot_ctl_3v3) > + regulator_disable(pcie->slot_ctl_3v3); > +} > + > static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, > bool en_hw_hot_rst) > { > @@ -1060,6 +1129,10 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, > return ret; > } > > + ret = tegra_pcie_enable_slot_regulators(pcie); > + if (ret < 0) > + goto fail_slot_reg_en; > + > ret = regulator_enable(pcie->pex_ctl_supply); > if (ret < 0) { > dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); > @@ -1142,6 +1215,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, > fail_core_clk: > regulator_disable(pcie->pex_ctl_supply); > fail_reg_en: > + tegra_pcie_disable_slot_regulators(pcie); > +fail_slot_reg_en: > tegra_pcie_bpmp_set_ctrl_state(pcie, false); > > return ret; > @@ -1174,6 +1249,8 @@ static int __deinit_controller(struct tegra_pcie_dw *pcie) > return ret; > } > > + tegra_pcie_disable_slot_regulators(pcie); > + > ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); > if (ret) { > dev_err(pcie->dev, "Failed to disable controller %d: %d\n", > @@ -1373,6 +1450,12 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) > return ret; > } > > + ret = tegra_pcie_get_slot_regulators(pcie); > + if (ret < 0) { > + dev_err(dev, "Failed to get slot regulators: %d\n", ret); > + return ret; > + } > + > pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); > if (IS_ERR(pcie->pex_ctl_supply)) { > dev_err(dev, "Failed to get regulator: %ld\n", > -- > 2.17.1 >
On Wed, Aug 28, 2019 at 10:58:49PM +0530, Vidya Sagar wrote: > Add support to configure PCIe C5's sideband signals PERST# and CLKREQ# > as output and bi-directional signals respectively which unlike other > PCIe controllers sideband signals are not configured by default. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> > --- > V3: > * None > > V2: > * None > > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++++++++++++++++++- > 1 file changed, 37 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > index adebbbf36bd0..3c0cf54f0aab 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > @@ -3,8 +3,9 @@ > #include <dt-bindings/gpio/tegra194-gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/mailbox/tegra186-hsp.h> > -#include <dt-bindings/reset/tegra194-reset.h> > +#include <dt-bindings/pinctrl/pinctrl-tegra.h> > #include <dt-bindings/power/tegra194-powergate.h> > +#include <dt-bindings/reset/tegra194-reset.h> > #include <dt-bindings/thermal/tegra194-bpmp-thermal.h> > > / { > @@ -130,6 +131,38 @@ > }; > }; > > + pinmux: pinmux@2430000 { > + compatible = "nvidia,tegra194-pinmux"; > + reg = <0x2430000 0x17000 > + 0xc300000 0x4000>; > + > + status = "okay"; > + > + pex_rst_c5_out_state: pex_rst_c5_out { > + pex_rst { > + nvidia,pins = "pex_l5_rst_n_pgg1"; > + nvidia,schmitt = <TEGRA_PIN_DISABLE>; > + nvidia,lpdr = <TEGRA_PIN_ENABLE>; > + nvidia,enable-input = <TEGRA_PIN_DISABLE>; > + nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + }; > + }; > + > + clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { > + clkreq { > + nvidia,pins = "pex_l5_clkreq_n_pgg0"; > + nvidia,schmitt = <TEGRA_PIN_DISABLE>; > + nvidia,lpdr = <TEGRA_PIN_ENABLE>; > + nvidia,enable-input = <TEGRA_PIN_ENABLE>; > + nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; > + nvidia,tristate = <TEGRA_PIN_DISABLE>; > + nvidia,pull = <TEGRA_PIN_PULL_NONE>; > + }; > + }; > + }; > + > uarta: serial@3100000 { > compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; > reg = <0x03100000 0x40>; > @@ -1365,6 +1398,9 @@ > num-viewport = <8>; > linux,pci-domain = <5>; > > + pinctrl-names = "default"; > + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; > + > clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, > <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; > clock-names = "core", "core_m"; > -- > 2.17.1 >
On Wed, Aug 28, 2019 at 10:58:50PM +0530, Vidya Sagar wrote: > Add 3.3V and 12V supplies regulators information of x16 PCIe slot in > p2972-0000 platform which is owned by C5 controller and also enable C5 > controller. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> > --- > V3: > * None > > V2: > * None > > .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++++++++++++++++ > .../boot/dts/nvidia/tegra194-p2972-0000.dts | 4 +++- > 2 files changed, 27 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi > index 62e07e1197cc..4c38426a6969 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi > @@ -289,5 +289,29 @@ > gpio = <&gpio TEGRA194_MAIN_GPIO(A, 3) GPIO_ACTIVE_HIGH>; > enable-active-high; > }; > + > + vdd_3v3_pcie: regulator@2 { > + compatible = "regulator-fixed"; > + reg = <2>; > + > + regulator-name = "PEX_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; > + regulator-boot-on; > + enable-active-high; > + }; > + > + vdd_12v_pcie: regulator@3 { > + compatible = "regulator-fixed"; > + reg = <3>; > + > + regulator-name = "VDD_12V"; > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + gpio = <&gpio TEGRA194_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; > + regulator-boot-on; > + enable-active-low; > + }; > }; > }; > diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts > index 23597d53c9c9..d47cd8c4dd24 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts > +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts > @@ -93,9 +93,11 @@ > }; > > pcie@141a0000 { > - status = "disabled"; > + status = "okay"; > > vddio-pex-ctl-supply = <&vdd_1v8ao>; > + vpcie3v3-supply = <&vdd_3v3_pcie>; > + vpcie12v-supply = <&vdd_12v_pcie>; > > phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, > <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, > -- > 2.17.1 >
On Wed, Aug 28, 2019 at 10:58:47PM +0530, Vidya Sagar wrote: > Add support to configure sideband signal pins when information is present > in respective controller's device-tree node. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > V3: > * Used 'dev' instead of 'pcie->dev' > > V2: > * Addressed review comment from Andrew Murray > * Handled failure case of pinctrl_pm_select_default_state() cleanly > > drivers/pci/controller/dwc/pcie-tegra194.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) Acked-by: Thierry Reding <treding@nvidia.com>
On Wed, Aug 28, 2019 at 10:58:48PM +0530, Vidya Sagar wrote: > Add support to get regulator information of 3.3V and 12V supplies of a PCIe > slot from the respective controller's device-tree node and enable those > supplies. This is required in platforms like p2972-0000 where the supplies > to x16 slot owned by C5 controller need to be enabled before attempting to > enumerate the devices. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > V3: > * Added a dev_err() print for failure case of tegra_pcie_get_slot_regulators() API > * Modified to make 100ms sleep valid only if at least one of the regulator handles exist > > V2: > * Addressed review comments from Thierry Reding and Andrew Murray > * Handled failure case of devm_regulator_get_optional() for -ENODEV cleanly > > drivers/pci/controller/dwc/pcie-tegra194.c | 83 ++++++++++++++++++++++ > 1 file changed, 83 insertions(+) Acked-by: Thierry Reding <treding@nvidia.com>
Hi Lorenzo / Bjorn, Can you please review this series? I have Reviewed-by and Acked-by from Rob, Thierry and Andrew already. Thanks, Vidya Sagar On 8/28/2019 10:58 PM, Vidya Sagar wrote: > This patch series enables Tegra194's C5 controller which owns x16 slot in > p2972-0000 platform. C5 controller's PERST# and CLKREQ# are not configured as > output and bi-directional signals by default and hence they need to be > configured explicitly. Also, x16 slot's 3.3V and 12V supplies are controlled > through GPIOs and hence they need to be enabled through regulator framework. > This patch series adds required infrastructural support to address both the > aforementioned requirements. > Testing done on p2972-0000 platform > - Able to enumerate devices connected to x16 slot (owned by C5 controller) > - Enumerated device's functionality verified > - Suspend-Resume sequence is verified with device connected to x16 slot > > V3: > * Addressed some more review comments from Andrew Murray and Thierry Reding > > V2: > * Changed the order of patches in the series for easy merging > * Addressed review comments from Thierry Reding and Andrew Murray > > Vidya Sagar (6): > dt-bindings: PCI: tegra: Add sideband pins configuration entries > dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries > PCI: tegra: Add support to configure sideband pins > PCI: tegra: Add support to enable slot regulators > arm64: tegra: Add configuration for PCIe C5 sideband signals > arm64: tegra: Add PCIe slot supply information in p2972-0000 platform > > .../bindings/pci/nvidia,tegra194-pcie.txt | 16 ++++ > .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++ > .../boot/dts/nvidia/tegra194-p2972-0000.dts | 4 +- > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++- > drivers/pci/controller/dwc/pcie-tegra194.c | 94 ++++++++++++++++++- > 5 files changed, 172 insertions(+), 4 deletions(-) >
On Thu, Sep 05, 2019 at 01:44:46PM +0530, Vidya Sagar wrote: > Hi Lorenzo / Bjorn, > Can you please review this series? > I have Reviewed-by and Acked-by from Rob, Thierry and Andrew already. Rebase it on top of my pci/tegra branch (it does not apply), resend it and I will merge it. Thanks, Lorenzo > Thanks, > Vidya Sagar > > On 8/28/2019 10:58 PM, Vidya Sagar wrote: > > This patch series enables Tegra194's C5 controller which owns x16 slot in > > p2972-0000 platform. C5 controller's PERST# and CLKREQ# are not configured as > > output and bi-directional signals by default and hence they need to be > > configured explicitly. Also, x16 slot's 3.3V and 12V supplies are controlled > > through GPIOs and hence they need to be enabled through regulator framework. > > This patch series adds required infrastructural support to address both the > > aforementioned requirements. > > Testing done on p2972-0000 platform > > - Able to enumerate devices connected to x16 slot (owned by C5 controller) > > - Enumerated device's functionality verified > > - Suspend-Resume sequence is verified with device connected to x16 slot > > > > V3: > > * Addressed some more review comments from Andrew Murray and Thierry Reding > > > > V2: > > * Changed the order of patches in the series for easy merging > > * Addressed review comments from Thierry Reding and Andrew Murray > > > > Vidya Sagar (6): > > dt-bindings: PCI: tegra: Add sideband pins configuration entries > > dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries > > PCI: tegra: Add support to configure sideband pins > > PCI: tegra: Add support to enable slot regulators > > arm64: tegra: Add configuration for PCIe C5 sideband signals > > arm64: tegra: Add PCIe slot supply information in p2972-0000 platform > > > > .../bindings/pci/nvidia,tegra194-pcie.txt | 16 ++++ > > .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++ > > .../boot/dts/nvidia/tegra194-p2972-0000.dts | 4 +- > > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++- > > drivers/pci/controller/dwc/pcie-tegra194.c | 94 ++++++++++++++++++- > > 5 files changed, 172 insertions(+), 4 deletions(-) > > >
On 9/5/2019 3:04 PM, Lorenzo Pieralisi wrote: > On Thu, Sep 05, 2019 at 01:44:46PM +0530, Vidya Sagar wrote: >> Hi Lorenzo / Bjorn, >> Can you please review this series? >> I have Reviewed-by and Acked-by from Rob, Thierry and Andrew already. > > Rebase it on top of my pci/tegra branch (it does not apply), > resend it and I will merge it. I just sent V4 after rebasing the series on top of pci/tegra. Thanks, Vidya Sagar > > Thanks, > Lorenzo > >> Thanks, >> Vidya Sagar >> >> On 8/28/2019 10:58 PM, Vidya Sagar wrote: >>> This patch series enables Tegra194's C5 controller which owns x16 slot in >>> p2972-0000 platform. C5 controller's PERST# and CLKREQ# are not configured as >>> output and bi-directional signals by default and hence they need to be >>> configured explicitly. Also, x16 slot's 3.3V and 12V supplies are controlled >>> through GPIOs and hence they need to be enabled through regulator framework. >>> This patch series adds required infrastructural support to address both the >>> aforementioned requirements. >>> Testing done on p2972-0000 platform >>> - Able to enumerate devices connected to x16 slot (owned by C5 controller) >>> - Enumerated device's functionality verified >>> - Suspend-Resume sequence is verified with device connected to x16 slot >>> >>> V3: >>> * Addressed some more review comments from Andrew Murray and Thierry Reding >>> >>> V2: >>> * Changed the order of patches in the series for easy merging >>> * Addressed review comments from Thierry Reding and Andrew Murray >>> >>> Vidya Sagar (6): >>> dt-bindings: PCI: tegra: Add sideband pins configuration entries >>> dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries >>> PCI: tegra: Add support to configure sideband pins >>> PCI: tegra: Add support to enable slot regulators >>> arm64: tegra: Add configuration for PCIe C5 sideband signals >>> arm64: tegra: Add PCIe slot supply information in p2972-0000 platform >>> >>> .../bindings/pci/nvidia,tegra194-pcie.txt | 16 ++++ >>> .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++ >>> .../boot/dts/nvidia/tegra194-p2972-0000.dts | 4 +- >>> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++- >>> drivers/pci/controller/dwc/pcie-tegra194.c | 94 ++++++++++++++++++- >>> 5 files changed, 172 insertions(+), 4 deletions(-) >>> >>