| Message ID | 20190821055530.8720-1-joel@jms.id.au |
|---|---|
| Headers | show |
| Series | ARM: Add ASPEED AST2600 support | expand |
On Wed, 21 Aug 2019, at 15:26, Joel Stanley wrote: > In preparation for adding the ast2600 which does not use this timer. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > --- > arch/arm/mach-aspeed/Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig > index a15c3a291386..2979aa4daeea 100644 > --- a/arch/arm/mach-aspeed/Kconfig > +++ b/arch/arm/mach-aspeed/Kconfig > @@ -5,7 +5,6 @@ menuconfig ARCH_ASPEED > select SRAM > select WATCHDOG > select ASPEED_WATCHDOG > - select FTTMR010_TIMER > select MFD_SYSCON > select PINCTRL > help > @@ -18,6 +17,7 @@ config MACH_ASPEED_G4 > depends on ARCH_MULTI_V5 > select CPU_ARM926T > select PINCTRL_ASPEED_G4 > + select FTTMR010_TIMER > help > Say yes if you intend to run on an Aspeed ast2400 or similar > fourth generation BMCs, such as those used by OpenPower Power8 > @@ -28,6 +28,7 @@ config MACH_ASPEED_G5 > depends on ARCH_MULTI_V6 > select CPU_V6 > select PINCTRL_ASPEED_G5 > + select FTTMR010_TIMER > help > Say yes if you intend to run on an Aspeed ast2500 or similar > fifth generation Aspeed BMCs. > -- > 2.23.0.rc1 > >
On Wed, 21 Aug 2019, at 15:26, Joel Stanley wrote: > The AST2600 is a Cortex A7 dual core CPU that uses the ARM GIC for > interrupts and ARM timer as a clocksource. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > --- > arch/arm/mach-aspeed/Kconfig | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig > index 2979aa4daeea..56007b0b6120 100644 > --- a/arch/arm/mach-aspeed/Kconfig > +++ b/arch/arm/mach-aspeed/Kconfig > @@ -1,7 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0-only > menuconfig ARCH_ASPEED > bool "Aspeed BMC architectures" > - depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 > + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 > select SRAM > select WATCHDOG > select ASPEED_WATCHDOG > @@ -33,4 +33,16 @@ config MACH_ASPEED_G5 > Say yes if you intend to run on an Aspeed ast2500 or similar > fifth generation Aspeed BMCs. > > +config MACH_ASPEED_G6 > + bool "Aspeed SoC 6th Generation" > + depends on ARCH_MULTI_V7 > + select CPU_V7 > + select PINCTRL_ASPEED_G6 > + select ARM_GIC > + select HAVE_ARM_ARCH_TIMER > + select HAVE_SMP > + help > + Say yes if you intend to run on an Aspeed ast2600 or similar > + sixth generation Aspeed BMCs. > + > endif > -- > 2.23.0.rc1 > >
On Wed, 21 Aug 2019, at 15:26, Joel Stanley wrote: > The AST2600 is a new SoC by ASPEED. It contains a dual core Cortex A7 > CPU and shares many periperhals with the existing AST2400 and AST2500. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/aspeed-ast2600-evb.dts | 44 ++++ > arch/arm/boot/dts/aspeed-g6.dtsi | 266 +++++++++++++++++++++++ > 3 files changed, 311 insertions(+) > create mode 100644 arch/arm/boot/dts/aspeed-ast2600-evb.dts > create mode 100644 arch/arm/boot/dts/aspeed-g6.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 247e556de48e..2d8d29e5686d 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1276,6 +1276,7 @@ dtb-$(CONFIG_ARCH_MILBEAUT) += > milbeaut-m10v-evb.dtb > dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb > dtb-$(CONFIG_ARCH_ASPEED) += \ > aspeed-ast2500-evb.dtb \ > + aspeed-ast2600-evb.dtb \ > aspeed-bmc-arm-centriq2400-rep.dtb \ > aspeed-bmc-arm-stardragon4800-rep2.dtb \ > aspeed-bmc-facebook-cmm.dtb \ > diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts > b/arch/arm/boot/dts/aspeed-ast2600-evb.dts > new file mode 100644 > index 000000000000..7f2528e084b5 > --- /dev/null > +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts > @@ -0,0 +1,44 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +// Copyright 2019 IBM Corp. > + > +/dts-v1/; > + > +#include "aspeed-g6.dtsi" > + > +/ { > + model = "AST2600 EVB"; > + compatible = "aspeed,ast2600"; > + > + aliases { > + serial4 = &uart5; > + }; > + > + chosen { > + bootargs = "console=ttyS4,115200n8"; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x80000000>; > + }; > +}; > + > +&mdio1 { > + status = "okay"; > + > + ethphy1: ethernet-phy@0 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + }; > +}; > + > +&mac1 { > + status = "okay"; > + > + phy-mode = "rgmii"; > + phy-handle = <ðphy1>; > +}; > + > +&emmc { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi > b/arch/arm/boot/dts/aspeed-g6.dtsi > new file mode 100644 > index 000000000000..9f9931541060 > --- /dev/null > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi > @@ -0,0 +1,266 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +// Copyright 2019 IBM Corp. > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/ast2600-clock.h> > + > +/ { > + model = "Aspeed BMC"; > + compatible = "aspeed,ast2600"; > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + aliases { > + serial4 = &uart5; > + }; > + > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "aspeed,ast2600-smp"; > + > + cpu@f00 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0xf00>; > + }; > + > + cpu@f01 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0xf01>; > + }; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; > + clocks = <&syscon ASPEED_CLK_HPLL>; > + arm,cpu-registers-not-fw-configured; > + }; > + > + ahb { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + device_type = "soc"; > + ranges; > + > + gic: interrupt-controller@40461000 { > + compatible = "arm,cortex-a7-gic"; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | > IRQ_TYPE_LEVEL_HIGH)>; > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupt-parent = <&gic>; > + reg = <0x40461000 0x1000>, > + <0x40462000 0x1000>, > + <0x40464000 0x2000>, > + <0x40466000 0x2000>; > + }; > + > + mdio0: mdio@1e650000 { > + compatible = "aspeed,ast2600-mdio"; > + reg = <0x1e650000 0x8>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + mdio1: mdio@1e650008 { > + compatible = "aspeed,ast2600-mdio"; > + reg = <0x1e650008 0x8>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + mdio2: mdio@1e650010 { > + compatible = "aspeed,ast2600-mdio"; > + reg = <0x1e650010 0x8>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + mdio3: mdio@1e650018 { > + compatible = "aspeed,ast2600-mdio"; > + reg = <0x1e650018 0x8>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + mac0: ftgmac@1e660000 { > + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; > + reg = <0x1e660000 0x180>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; > + status = "disabled"; > + }; > + > + mac1: ftgmac@1e680000 { > + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; > + reg = <0x1e680000 0x180>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; > + status = "disabled"; > + }; > + > + mac2: ftgmac@1e670000 { > + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; > + reg = <0x1e670000 0x180>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; > + status = "disabled"; > + }; > + > + mac3: ftgmac@1e690000 { > + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; > + reg = <0x1e690000 0x180>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; > + status = "disabled"; > + }; > + > + apb { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + syscon: syscon@1e6e2000 { > + compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; > + reg = <0x1e6e2000 0x1000>; > + ranges = <0 0x1e6e2000 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + > + pinctrl: pinctrl { > + compatible = "aspeed,ast2600-pinctrl"; > + }; > + > + smp-memram@180 { > + compatible = "aspeed,ast2600-smpmem"; > + reg = <0x180 0x40>; > + }; > + }; > + > + rng: hwrng@1e6e2524 { > + compatible = "timeriomem_rng"; > + reg = <0x1e6e2524 0x4>; > + period = <1>; > + quality = <100>; > + }; > + > + rtc: rtc@1e781000 { > + compatible = "aspeed,ast2600-rtc"; > + reg = <0x1e781000 0x18>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + uart5: serial@1e784000 { > + compatible = "ns16550a"; > + reg = <0x1e784000 0x1000>; > + reg-shift = <2>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; > + no-loopback-test; > + }; > + > + wdt1: watchdog@1e785000 { > + compatible = "aspeed,ast2600-wdt"; > + reg = <0x1e785000 0x40>; > + }; > + > + wdt2: watchdog@1e785040 { > + compatible = "aspeed,ast2600-wdt"; > + reg = <0x1e785040 0x40>; > + status = "disabled"; > + }; > + > + wdt3: watchdog@1e785080 { > + compatible = "aspeed,ast2600-wdt"; > + reg = <0x1e785080 0x40>; > + status = "disabled"; > + }; > + > + wdt4: watchdog@1e7850C0 { > + compatible = "aspeed,ast2600-wdt"; > + reg = <0x1e7850C0 0x40>; > + status = "disabled"; > + }; > + > + sdc: sdc@1e740000 { > + compatible = "aspeed,ast2600-sd-controller"; > + reg = <0x1e740000 0x100>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x1e740000 0x10000>; > + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; > + status = "disabled"; > + > + sdhci0: sdhci@1e740100 { > + compatible = "aspeed,ast2600-sdhci", "sdhci"; > + reg = <0x100 0x100>; > + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; > + sdhci,auto-cmd12; > + clocks = <&syscon ASPEED_CLK_SDIO>; > + status = "disabled"; > + }; > + > + sdhci1: sdhci@1e740200 { > + compatible = "aspeed,ast2600-sdhci", "sdhci"; > + reg = <0x200 0x100>; > + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; > + sdhci,auto-cmd12; > + clocks = <&syscon ASPEED_CLK_SDIO>; > + status = "disabled"; > + }; > + }; > + > + emmc: sdc@1e750000 { > + compatible = "aspeed,ast2600-sd-controller"; > + reg = <0x1e750000 0x100>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x1e750000 0x10000>; > + clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>; > + status = "disabled"; > + > + sdhci@1e750100 { > + compatible = "aspeed,ast2600-sdhci"; > + reg = <0x100 0x100>; > + sdhci,auto-cmd12; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&syscon ASPEED_CLK_EMMC>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_emmc_default>; > + }; > + }; > + }; > + }; > +}; > + > +&pinctrl { > + pinctrl_emmc_default: emmc_default { > + function = "SD3"; > + groups = "SD3"; > + }; I need to send some fixes for pinmux along with the dt patche, but this will do for the moment. Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
On Wed, 21 Aug 2019, at 15:26, Joel Stanley wrote: > This adds the ASPEED AST2600 system and associated ASPEED devices so we > get build coverage. > > The changes to the UART configuration to ensure the default console > (UART5) works. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Acked-by: Andrew Jeffery <andrew@aj.id.au>
On Wed, 21 Aug 2019, at 15:26, Joel Stanley wrote: > CONFIG_STRICT_KERNEL_RWX is enabled by default with ARMv7. > > Turn on HIGHMEM as the EVB has 2GB of RAM, and not all is usable without > hihgmem. > > The SoC contains Cortex A7 supporting VFP and has two CPUs. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/configs/aspeed_g5_defconfig | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/configs/aspeed_g5_defconfig > b/arch/arm/configs/aspeed_g5_defconfig > index 426d8e0c9890..597536cc9573 100644 > --- a/arch/arm/configs/aspeed_g5_defconfig > +++ b/arch/arm/configs/aspeed_g5_defconfig > @@ -21,21 +21,26 @@ CONFIG_PERF_EVENTS=y > CONFIG_SLAB=y > CONFIG_SLAB_FREELIST_RANDOM=y > CONFIG_ARCH_MULTI_V6=y > -# CONFIG_ARCH_MULTI_V7 is not set > CONFIG_ARCH_ASPEED=y > CONFIG_MACH_ASPEED_G5=y > +CONFIG_MACH_ASPEED_G6=y > # CONFIG_CACHE_L2X0 is not set > +CONFIG_SMP=y > +# CONFIG_ARM_CPU_TOPOLOGY is not set > CONFIG_VMSPLIT_2G=y > +CONFIG_NR_CPUS=2 > +CONFIG_HIGHMEM=y > CONFIG_UACCESS_WITH_MEMCPY=y > CONFIG_SECCOMP=y > # CONFIG_ATAGS is not set > CONFIG_ZBOOT_ROM_TEXT=0x0 > CONFIG_ZBOOT_ROM_BSS=0x0 > CONFIG_KEXEC=y > -# CONFIG_SUSPEND is not set > +CONFIG_VFP=y > +CONFIG_NEON=y > +CONFIG_KERNEL_MODE_NEON=y > CONFIG_FIRMWARE_MEMMAP=y > CONFIG_JUMP_LABEL=y > -CONFIG_STRICT_KERNEL_RWX=y > # CONFIG_BLK_DEV_BSG is not set > # CONFIG_BLK_DEBUG_FS is not set > # CONFIG_MQ_IOSCHED_DEADLINE is not set > @@ -140,10 +145,12 @@ CONFIG_ASPEED_BT_IPMI_BMC=y > CONFIG_HW_RANDOM_TIMERIOMEM=y > # CONFIG_I2C_COMPAT is not set > CONFIG_I2C_CHARDEV=y > +CONFIG_I2C_MUX=y > CONFIG_I2C_MUX_PCA9541=y > CONFIG_I2C_MUX_PCA954x=y > CONFIG_I2C_ASPEED=y > CONFIG_I2C_FSI=y > +CONFIG_SPI=y > CONFIG_GPIOLIB=y > CONFIG_GPIO_SYSFS=y > CONFIG_GPIO_ASPEED=y > @@ -194,6 +201,10 @@ CONFIG_USB_CONFIGFS_F_LB_SS=y > CONFIG_USB_CONFIGFS_F_FS=y > CONFIG_USB_CONFIGFS_F_HID=y > CONFIG_USB_CONFIGFS_F_PRINTER=y > +CONFIG_MMC=y > +CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_PLTFM=y > +CONFIG_MMC_SDHCI_OF_ASPEED=y The patches haven't yet been applied to the MMC tree, maybe we should add this later? Anyway, Acked-by: Andrew Jeffery <andrew@aj.id.au>
On Thu, 22 Aug 2019 at 02:07, Andrew Jeffery <andrew@aj.id.au> wrote: > > +CONFIG_MMC=y > > +CONFIG_MMC_SDHCI=y > > +CONFIG_MMC_SDHCI_PLTFM=y > > +CONFIG_MMC_SDHCI_OF_ASPEED=y > > The patches haven't yet been applied to the MMC tree, maybe we should > add this later? When enabling drivers in the same merge window as they go into the tree we will always be in this situation. If the driver doesn't make it in this merge window, or first has has changes, the worst that will happen is the kconfig name changes and I need to update it later. I think we're safe to include it as-is. Thanks for the review. Cheers, Joel
On Thu, Aug 22, 2019 at 6:43 AM Joel Stanley <joel@jms.id.au> wrote: > > On Thu, 22 Aug 2019 at 02:07, Andrew Jeffery <andrew@aj.id.au> wrote: > > > +CONFIG_MMC=y > > > +CONFIG_MMC_SDHCI=y > > > +CONFIG_MMC_SDHCI_PLTFM=y > > > +CONFIG_MMC_SDHCI_OF_ASPEED=y > > > > The patches haven't yet been applied to the MMC tree, maybe we should > > add this later? > > When enabling drivers in the same merge window as they go into the > tree we will always be in this situation. > > If the driver doesn't make it in this merge window, or first has has > changes, the worst that will happen is the kconfig name changes and I > need to update it later. I think we're safe to include it as-is. Yes, that's fine. Please also enable all the drivers you need in multi_v7_defconfig now, preferably as loadable modules. Arnd