| Message ID | 1563184103-8493-1-git-send-email-peng.fan@nxp.com |
|---|---|
| Headers | show |
| Series | mailbox: arm: introduce smc triggered mailbox | expand |
Hi All, > Subject: [PATCH v3 2/2] mailbox: introduce ARM SMC based mailbox Any comments with this patch? > > From: Peng Fan <peng.fan@nxp.com> > > This mailbox driver implements a mailbox which signals transmitted data via > an ARM smc (secure monitor call) instruction. The mailbox receiver is > implemented in firmware and can synchronously return data when it returns > execution to the non-secure world again. > An asynchronous receive path is not implemented. > This allows the usage of a mailbox to trigger firmware actions on SoCs which > either don't have a separate management processor or on which such a core > is not available. A user of this mailbox could be the SCP interface. > > Modified from Andre Przywara's v2 patch > https://lore.kernel.org/patchwork/patch/812999/ > > Cc: Andre Przywara <andre.przywara@arm.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > > V3: > Drop interrupt. > Introduce transports for mem/reg usage. > Add chan-id for mem usage. > > V2: > Add interrupts notification support. > > drivers/mailbox/Kconfig | 7 ++ > drivers/mailbox/Makefile | 2 + > drivers/mailbox/arm-smc-mailbox.c | 215 > ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 224 insertions(+) > create mode 100644 drivers/mailbox/arm-smc-mailbox.c > > diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index > 595542bfae85..c3bd0f1ddcd8 100644 > --- a/drivers/mailbox/Kconfig > +++ b/drivers/mailbox/Kconfig > @@ -15,6 +15,13 @@ config ARM_MHU > The controller has 3 mailbox channels, the last of which can be > used in Secure mode only. > > +config ARM_SMC_MBOX > + tristate "Generic ARM smc mailbox" > + depends on OF && HAVE_ARM_SMCCC > + help > + Generic mailbox driver which uses ARM smc calls to call into > + firmware for triggering mailboxes. > + > config IMX_MBOX > tristate "i.MX Mailbox" > depends on ARCH_MXC || COMPILE_TEST > diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index > c22fad6f696b..93918a84c91b 100644 > --- a/drivers/mailbox/Makefile > +++ b/drivers/mailbox/Makefile > @@ -7,6 +7,8 @@ obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o > > obj-$(CONFIG_ARM_MHU) += arm_mhu.o > > +obj-$(CONFIG_ARM_SMC_MBOX) += arm-smc-mailbox.o > + > obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o > > obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += > armada-37xx-rwtm-mailbox.o > diff --git a/drivers/mailbox/arm-smc-mailbox.c > b/drivers/mailbox/arm-smc-mailbox.c > new file mode 100644 > index 000000000000..76a2ae11ee4d > --- /dev/null > +++ b/drivers/mailbox/arm-smc-mailbox.c > @@ -0,0 +1,215 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2016,2017 ARM Ltd. > + * Copyright 2019 NXP > + */ > + > +#include <linux/arm-smccc.h> > +#include <linux/device.h> > +#include <linux/kernel.h> > +#include <linux/interrupt.h> > +#include <linux/mailbox_controller.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > + > +#define ARM_SMC_MBOX_MEM_TRANS BIT(0) > + > +struct arm_smc_chan_data { > + u32 function_id; > + u32 chan_id; > + u32 flags; > +}; > + > +struct arm_smccc_mbox_cmd { > + unsigned long a0, a1, a2, a3, a4, a5, a6, a7; }; > + > +typedef unsigned long (smc_mbox_fn)(unsigned long, unsigned long, > + unsigned long, unsigned long, > + unsigned long, unsigned long, > + unsigned long, unsigned long); > +static smc_mbox_fn *invoke_smc_mbox_fn; > + > +static int arm_smc_send_data(struct mbox_chan *link, void *data) { > + struct arm_smc_chan_data *chan_data = link->con_priv; > + struct arm_smccc_mbox_cmd *cmd = data; > + unsigned long ret; > + u32 function_id; > + u32 chan_id; > + > + if (chan_data->flags & ARM_SMC_MBOX_MEM_TRANS) { > + if (chan_data->function_id != UINT_MAX) > + function_id = chan_data->function_id; > + else > + function_id = cmd->a0; > + chan_id = chan_data->chan_id; > + ret = invoke_smc_mbox_fn(function_id, chan_id, 0, 0, 0, 0, > + 0, 0); > + } else { > + ret = invoke_smc_mbox_fn(cmd->a0, cmd->a1, cmd->a2, cmd->a3, > + cmd->a4, cmd->a5, cmd->a6, cmd->a7); > + } > + > + mbox_chan_received_data(link, (void *)ret); > + > + return 0; > +} > + > +static unsigned long __invoke_fn_hvc(unsigned long function_id, > + unsigned long arg0, unsigned long arg1, > + unsigned long arg2, unsigned long arg3, > + unsigned long arg4, unsigned long arg5, > + unsigned long arg6) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_hvc(function_id, arg0, arg1, arg2, arg3, arg4, > + arg5, arg6, &res); > + return res.a0; > +} > + > +static unsigned long __invoke_fn_smc(unsigned long function_id, > + unsigned long arg0, unsigned long arg1, > + unsigned long arg2, unsigned long arg3, > + unsigned long arg4, unsigned long arg5, > + unsigned long arg6) > +{ > + struct arm_smccc_res res; > + > + arm_smccc_smc(function_id, arg0, arg1, arg2, arg3, arg4, > + arg5, arg6, &res); > + return res.a0; > +} > + > +static const struct mbox_chan_ops arm_smc_mbox_chan_ops = { > + .send_data = arm_smc_send_data, > +}; > + > +static int arm_smc_mbox_probe(struct platform_device *pdev) { > + struct device *dev = &pdev->dev; > + struct mbox_controller *mbox; > + struct arm_smc_chan_data *chan_data; > + const char *method; > + bool mem_trans = false; > + int ret, i; > + u32 val; > + > + if (!of_property_read_u32(dev->of_node, "arm,num-chans", &val)) { > + if (!val) { > + dev_err(dev, "invalid arm,num-chans value %u\n", val); > + return -EINVAL; > + } > + } else { > + return -EINVAL; > + } > + > + if (!of_property_read_string(dev->of_node, "transports", &method)) { > + if (!strcmp("mem", method)) { > + mem_trans = true; > + } else if (!strcmp("reg", method)) { > + mem_trans = false; > + } else { > + dev_warn(dev, "invalid \"transports\" property: %s\n", > + method); > + > + return -EINVAL; > + } > + } else { > + return -EINVAL; > + } > + > + if (!of_property_read_string(dev->of_node, "method", &method)) { > + if (!strcmp("hvc", method)) { > + invoke_smc_mbox_fn = __invoke_fn_hvc; > + } else if (!strcmp("smc", method)) { > + invoke_smc_mbox_fn = __invoke_fn_smc; > + } else { > + dev_warn(dev, "invalid \"method\" property: %s\n", > + method); > + > + return -EINVAL; > + } > + } else { > + return -EINVAL; > + } > + > + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); > + if (!mbox) > + return -ENOMEM; > + > + mbox->num_chans = val; > + mbox->chans = devm_kcalloc(dev, mbox->num_chans, > sizeof(*mbox->chans), > + GFP_KERNEL); > + if (!mbox->chans) > + return -ENOMEM; > + > + chan_data = devm_kcalloc(dev, mbox->num_chans, sizeof(*chan_data), > + GFP_KERNEL); > + if (!chan_data) > + return -ENOMEM; > + > + for (i = 0; i < mbox->num_chans; i++) { > + u32 function_id; > + > + ret = of_property_read_u32_index(dev->of_node, > + "arm,func-ids", i, > + &function_id); > + if (ret) > + chan_data[i].function_id = UINT_MAX; > + > + else > + chan_data[i].function_id = function_id; > + > + chan_data[i].chan_id = i; > + > + if (mem_trans) > + chan_data[i].flags |= ARM_SMC_MBOX_MEM_TRANS; > + mbox->chans[i].con_priv = &chan_data[i]; > + } > + > + mbox->txdone_poll = false; > + mbox->txdone_irq = false; > + mbox->ops = &arm_smc_mbox_chan_ops; > + mbox->dev = dev; > + > + platform_set_drvdata(pdev, mbox); > + > + ret = devm_mbox_controller_register(dev, mbox); > + if (ret) > + return ret; > + > + dev_info(dev, "ARM SMC mailbox enabled with %d chan%s.\n", > + mbox->num_chans, mbox->num_chans == 1 ? "" : "s"); > + > + return ret; > +} > + > +static int arm_smc_mbox_remove(struct platform_device *pdev) { > + struct mbox_controller *mbox = platform_get_drvdata(pdev); > + > + mbox_controller_unregister(mbox); > + return 0; > +} > + > +static const struct of_device_id arm_smc_mbox_of_match[] = { > + { .compatible = "arm,smc-mbox", }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, arm_smc_mbox_of_match); > + > +static struct platform_driver arm_smc_mbox_driver = { > + .driver = { > + .name = "arm-smc-mbox", > + .of_match_table = arm_smc_mbox_of_match, > + }, > + .probe = arm_smc_mbox_probe, > + .remove = arm_smc_mbox_remove, > +}; > +module_platform_driver(arm_smc_mbox_driver); > + > +MODULE_AUTHOR("Andre Przywara <andre.przywara@arm.com>"); > +MODULE_DESCRIPTION("Generic ARM smc mailbox driver"); > +MODULE_LICENSE("GPL v2"); Thanks, Peng. > -- > 2.16.4
From: Peng Fan <peng.fan@nxp.com> V3: Drop interrupt Introduce transports for mem/reg usage Add chan-id for mem usage Convert to yaml format V2: This is a modified version from Andre Przywara's patch series https://lore.kernel.org/patchwork/cover/812997/. The modification are mostly: Introduce arm,num-chans Introduce arm_smccc_mbox_cmd txdone_poll and txdone_irq are both set to false arm,func-ids are kept, but as an optional property. Rewords SCPI to SCMI, because I am trying SCMI over SMC, not SCPI. Introduce interrupts notification. [1] is a draft implementation of i.MX8MM SCMI ATF implementation that use smc as mailbox, power/clk is included, but only part of clk has been implemented to work with hardware, power domain only supports get name for now. The traditional Linux mailbox mechanism uses some kind of dedicated hardware IP to signal a condition to some other processing unit, typically a dedicated management processor. This mailbox feature is used for instance by the SCMI protocol to signal a request for some action to be taken by the management processor. However some SoCs does not have a dedicated management core to provide those services. In order to service TEE and to avoid linux shutdown power and clock that used by TEE, need let firmware to handle power and clock, the firmware here is ARM Trusted Firmware that could also run SCMI service. The existing SCMI implementation uses a rather flexible shared memory region to communicate commands and their parameters, it still requires a mailbox to actually trigger the action. This patch series provides a Linux mailbox compatible service which uses smc calls to invoke firmware code, for instance taking care of SCMI requests. The actual requests are still communicated using the standard SCMI way of shared memory regions, but a dedicated mailbox hardware IP can be replaced via this new driver. This simple driver uses the architected SMC calling convention to trigger firmware services, also allows for using "HVC" calls to call into hypervisors or firmware layers running in the EL2 exception level. Patch 1 contains the device tree binding documentation, patch 2 introduces the actual mailbox driver. Please note that this driver just provides a generic mailbox mechanism, It could support synchronous TX/RX, or synchronous TX with asynchronous RX. And while providing SCMI services was the reason for this exercise, this driver is in no way bound to this use case, but can be used generically where the OS wants to signal a mailbox condition to firmware or a hypervisor. Also the driver is in no way meant to replace any existing firmware interface, but actually to complement existing interfaces. [1] https://github.com/MrVan/arm-trusted-firmware/tree/scmi Peng Fan (2): dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox mailbox: introduce ARM SMC based mailbox .../devicetree/bindings/mailbox/arm-smc.yaml | 124 ++++++++++++ drivers/mailbox/Kconfig | 7 + drivers/mailbox/Makefile | 2 + drivers/mailbox/arm-smc-mailbox.c | 215 +++++++++++++++++++++ 4 files changed, 348 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.yaml create mode 100644 drivers/mailbox/arm-smc-mailbox.c