| Message ID | 20190708035243.12170-1-s-anna@ti.com |
|---|---|
| Headers | show |
| Series | Add TI PRUSS Local Interrupt Controller IRQChip driver | expand |
On 7/7/19 10:52 PM, Suman Anna wrote: > The PRUSS INTC receives a number of system input interrupt source events > and supports individual control configuration and hardware prioritization. > These input events can be mapped to some output host interrupts through 2 > levels of many-to-one mapping i.e. events to channel mapping and channels > to host interrupts. > > This mapping information is provided through the PRU firmware that is > loaded onto a PRU core/s or through the device tree node of the PRU What will the device tree bindings for this look like? Looking back at Rob's comment on the initial series [1], I still think that increasing the #interrupt-cells sounds like a reasonable solution. [1]: https://patchwork.kernel.org/patch/10697705/#22375155 > application. The mapping is configured by the PRU remoteproc driver, and > is setup before the PRU core is started and cleaned up after the PRU core > is stopped. This event mapping configuration logic is optimized to program > the Channel Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) > only when a new program is being loaded/started and simply disables the > same events and interrupt channels without zeroing out the corresponding > map registers when stopping a PRU. > > Add two helper functions: pruss_intc_configure() & pruss_intc_unconfigure() > that the PRU remoteproc driver can use to configure the PRUSS INTC. > > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: Andrew F. Davis <afd@ti.com> > Signed-off-by: Roger Quadros <rogerq@ti.com> > --- > drivers/irqchip/irq-pruss-intc.c | 258 ++++++++++++++++++++++++- > include/linux/irqchip/irq-pruss-intc.h | 33 ++++ > 2 files changed, 289 insertions(+), 2 deletions(-) > create mode 100644 include/linux/irqchip/irq-pruss-intc.h > > diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c > index 142d01b434e0..8118c2a2ac43 100644 > --- a/drivers/irqchip/irq-pruss-intc.c > +++ b/drivers/irqchip/irq-pruss-intc.c > @@ -9,6 +9,7 @@ > > #include <linux/irq.h> > #include <linux/irqchip/chained_irq.h> > +#include <linux/irqchip/irq-pruss-intc.h> > #include <linux/irqdomain.h> > #include <linux/module.h> > #include <linux/of_device.h> > @@ -24,8 +25,8 @@ > /* minimum starting host interrupt number for MPU */ > #define MIN_PRU_HOST_INT 2 > > -/* maximum number of system events */ > -#define MAX_PRU_SYS_EVENTS 64 > +/* maximum number of host interrupts */ > +#define MAX_PRU_HOST_INT 10 > > /* PRU_ICSS_INTC registers */ > #define PRU_INTC_REVID 0x0000 > @@ -57,15 +58,29 @@ > #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) > #define PRU_INTC_HIER 0x1500 > > +/* CMR register bit-field macros */ > +#define CMR_EVT_MAP_MASK 0xf > +#define CMR_EVT_MAP_BITS 8 > +#define CMR_EVT_PER_REG 4 > + > +/* HMR register bit-field macros */ > +#define HMR_CH_MAP_MASK 0xf > +#define HMR_CH_MAP_BITS 8 > +#define HMR_CH_PER_REG 4 > + > /* HIPIR register bit-fields */ > #define INTC_HIPIR_NONE_HINT 0x80000000 > > +/* use -1 to mark unassigned events and channels */ > +#define FREE -1 It could be helpful to have this macro in the public header. > + > /** > * struct pruss_intc - PRUSS interrupt controller structure > * @irqs: kernel irq numbers corresponding to PRUSS host interrupts > * @base: base virtual address of INTC register space > * @irqchip: irq chip for this interrupt controller > * @domain: irq domain for this interrupt controller > + * @config_map: stored INTC configuration mapping data > * @lock: mutex to serialize access to INTC > * @host_mask: indicate which HOST IRQs are enabled > * @shared_intr: bit-map denoting if the MPU host interrupt is shared > @@ -76,6 +91,7 @@ struct pruss_intc { > void __iomem *base; > struct irq_chip *irqchip; > struct irq_domain *domain; > + struct pruss_intc_config config_map; > struct mutex lock; /* PRUSS INTC lock */ > u32 host_mask; > u16 shared_intr; > @@ -107,6 +123,238 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, > return 0; > } > > +static struct pruss_intc *to_pruss_intc(struct device *pru_dev) > +{ > + struct device_node *np; > + struct platform_device *pdev; > + struct device *pruss_dev = pru_dev->parent; > + struct pruss_intc *intc = ERR_PTR(-ENODEV); > + > + np = of_get_child_by_name(pruss_dev->of_node, "interrupt-controller"); > + if (!np) { > + dev_err(pruss_dev, "pruss does not have an interrupt-controller node\n"); > + return intc; > + } > + > + pdev = of_find_device_by_node(np); > + if (!pdev) { > + dev_err(pruss_dev, "no associated platform device\n"); > + goto out; > + } > + > + intc = platform_get_drvdata(pdev); > + if (!intc) { > + dev_err(pruss_dev, "pruss intc device probe failed?\n"); > + intc = ERR_PTR(-EINVAL); > + } > + > +out: > + of_node_put(np); > + return intc; > +} > + > +/** > + * pruss_intc_configure() - configure the PRUSS INTC > + * @dev: pru device pointer > + * @intc_config: PRU core-specific INTC configuration > + * > + * Configures the PRUSS INTC with the provided configuration from > + * a PRU core. Any existing event to channel mappings or channel to > + * host interrupt mappings are checked to make sure there are no > + * conflicting configuration between both the PRU cores. The function > + * is intended to be used only by the PRU remoteproc driver. > + * > + * Returns 0 on success, or a suitable error code otherwise > + */ > +int pruss_intc_configure(struct device *dev, It seems like this would be easier to use if it took an IRQ number or struct irq_data * as a parameter instead of struct device *. My line of thinking is that callers of this function will already be calling some variant of request_irq() so they will already have this info. It would cut out the pointer acrobatics in to_pruss_intc. > + struct pruss_intc_config *intc_config) > +{ > + struct pruss_intc *intc; > + int i, idx, ret; > + s8 ch, host; > + u64 sysevt_mask = 0; > + u32 ch_mask = 0; > + u32 host_mask = 0; > + u32 val; > + > + intc = to_pruss_intc(dev); > + if (IS_ERR(intc)) > + return PTR_ERR(intc); > + > + mutex_lock(&intc->lock); > + > + /* > + * configure channel map registers - each register holds map info > + * for 4 events, with each event occupying the lower nibble in > + * a register byte address in little-endian fashion > + */ > + for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { > + ch = intc_config->sysev_to_ch[i]; > + if (ch < 0) > + continue; > + > + /* check if sysevent already assigned */ > + if (intc->config_map.sysev_to_ch[i] != FREE) { > + dev_err(dev, "event %d (req. channel %d) already assigned to channel %d\n", > + i, ch, intc->config_map.sysev_to_ch[i]); > + ret = -EEXIST; > + goto unlock; If we fail here, shouldn't we unwind any previous mappings made? Otherwise, if we try to map the same event again, it will show as in use, even though it is not in use. > + } > + > + intc->config_map.sysev_to_ch[i] = ch; > + > + idx = i / CMR_EVT_PER_REG; > + val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); > + val &= ~(CMR_EVT_MAP_MASK << > + ((i % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS)); > + val |= ch << ((i % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS); > + pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); > + sysevt_mask |= BIT_ULL(i); > + ch_mask |= BIT(ch); > + > + dev_dbg(dev, "SYSEV%d -> CH%d (CMR%d 0x%08x)\n", i, ch, idx, > + pruss_intc_read_reg(intc, PRU_INTC_CMR(idx))); > + } > + > + /* > + * set host map registers - each register holds map info for > + * 4 channels, with each channel occupying the lower nibble in > + * a register byte address in little-endian fashion > + */ > + for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { > + host = intc_config->ch_to_host[i]; > + if (host < 0) > + continue; > + > + /* check if channel already assigned */ > + if (intc->config_map.ch_to_host[i] != FREE) { > + dev_err(dev, "channel %d (req. intr_no %d) already assigned to intr_no %d\n", > + i, host, intc->config_map.ch_to_host[i]); > + ret = -EEXIST; > + goto unlock; Same comment about unwinding here and below. > + } > + > + /* check if host intr is already in use by other PRU */ It seems like there would be use cases where someone might want to map multiple PRU system events, and therefore multiple channels, to a single host interrupt. > + if (intc->host_mask & (1U << host)) { > + dev_err(dev, "%s: host intr %d already in use\n", > + __func__, host); > + ret = -EEXIST; > + goto unlock; > + } > + --snip-- > diff --git a/include/linux/irqchip/irq-pruss-intc.h b/include/linux/irqchip/irq-pruss-intc.h > new file mode 100644 > index 000000000000..f1f1bb150100 > --- /dev/null > +++ b/include/linux/irqchip/irq-pruss-intc.h > @@ -0,0 +1,33 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * PRU-ICSS sub-system private interfaces > + * > + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ > + * Suman Anna <s-anna@ti.com> > + */ > + > +#ifndef __LINUX_IRQ_PRUSS_INTC_H > +#define __LINUX_IRQ_PRUSS_INTC_H > + > +/* maximum number of system events */ > +#define MAX_PRU_SYS_EVENTS 64 > + > +/* maximum number of interrupt channels */ > +#define MAX_PRU_CHANNELS 10 > + > +/** > + * struct pruss_intc_config - INTC configuration info > + * @sysev_to_ch: system events to channel mapping information > + * @ch_to_host: interrupt channel to host interrupt information > + */ > +struct pruss_intc_config { > + s8 sysev_to_ch[MAX_PRU_SYS_EVENTS]; > + s8 ch_to_host[MAX_PRU_CHANNELS]; > +}; > + > +int pruss_intc_configure(struct device *dev, > + struct pruss_intc_config *intc_config); > +int pruss_intc_unconfigure(struct device *dev, > + struct pruss_intc_config *intc_config); > + > +#endif /* __LINUX_IRQ_PRUSS_INTC_H */ > FYI, on AM18xx, events 0 to 31 can be muxed via CFGCHIP3[3].PRUSSEVTSEL so an additional bit of information will be needed in this struct for the mux selection. I don't see a probably with adding that later though.
On 7/7/19 10:52 PM, Suman Anna wrote: > From: "Andrew F. Davis" <afd@ti.com> > > The Programmable Real-Time Unit Subsystem (PRUSS) contains a local > interrupt controller (INTC) that can handle various system input events > and post interrupts back to the device-level initiators. The INTC can > support upto 64 input events with individual control configuration and > hardware prioritization. These events are mapped onto 10 output interrupt > lines through two levels of many-to-one mapping support. Different > interrupt lines are routed to the individual PRU cores or to the host > CPU, or to other devices on the SoC. Some of these events are sourced > from peripherals or other sub-modules within that PRUSS, while a few > others are sourced from SoC-level peripherals/devices. > > The PRUSS INTC platform driver manages this PRUSS interrupt controller > and implements an irqchip driver to provide a Linux standard way for > the PRU client users to enable/disable/ack/re-trigger a PRUSS system > event. The system events to interrupt channels and host interrupts > relies on the mapping configuration provided either through the PRU > firmware blob or via the PRU application's device tree node. The > mappings will be programmed during the boot/shutdown of a PRU core. > > The PRUSS INTC module is reference counted during the interrupt > setup phase through the irqchip's irq_request_resources() and > irq_release_resources() ops. This restricts the module from being > removed as long as there are active interrupt users. > > The driver currently supports and can be built for OMAP architecture > based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based > 66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs. > All of these SoCs support 64 system events, 10 interrupt channels and > 10 output interrupt lines per PRUSS INTC with a few SoC integration > differences. > > NOTE: > Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that > enables multiple external events to be routed to a specific number > of input interrupt events. Any non-default external interrupt event > directed towards PRUSS needs this crossbar to be setup properly. The all of the explanations above are very helpful. Great work. > > Signed-off-by: Andrew F. Davis <afd@ti.com> > Signed-off-by: Suman Anna <s-anna@ti.com> > Signed-off-by: Roger Quadros <rogerq@ti.com> > --- > Prior version: https://patchwork.kernel.org/patch/10795761/ > > drivers/irqchip/Kconfig | 10 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-pruss-intc.c | 352 +++++++++++++++++++++++++++++++ > 3 files changed, 363 insertions(+) > create mode 100644 drivers/irqchip/irq-pruss-intc.c > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig > index 659c5e0fb835..b0a9479d527c 100644 > --- a/drivers/irqchip/Kconfig > +++ b/drivers/irqchip/Kconfig > @@ -447,6 +447,16 @@ config TI_SCI_INTA_IRQCHIP > If you wish to use interrupt aggregator irq resources managed by the > TI System Controller, say Y here. Otherwise, say N. > > +config TI_PRUSS_INTC > + tristate "TI PRU-ICSS Interrupt Controller" > + depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE > + select IRQ_DOMAIN > + help > + This enables support for the PRU-ICSS Local Interrupt Controller > + present within a PRU-ICSS subsystem present on various TI SoCs. > + The PRUSS INTC enables various interrupts to be routed to multiple > + different processors within the SoC. > + > endmenu > > config SIFIVE_PLIC > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile > index 606a003a0000..717f1d49e549 100644 > --- a/drivers/irqchip/Makefile > +++ b/drivers/irqchip/Makefile > @@ -100,3 +100,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o > obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o > obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o > obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o > +obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o > diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c > new file mode 100644 > index 000000000000..d62186ad1be4 > --- /dev/null > +++ b/drivers/irqchip/irq-pruss-intc.c > @@ -0,0 +1,352 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * PRU-ICSS INTC IRQChip driver for various TI SoCs > + * > + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ > + * Andrew F. Davis <afd@ti.com> > + * Suman Anna <s-anna@ti.com> > + */ > + > +#include <linux/irq.h> > +#include <linux/irqchip/chained_irq.h> > +#include <linux/irqdomain.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > + > +/* > + * Number of host interrupts reaching the main MPU sub-system. Note that this > + * is not the same as the total number of host interrupts supported by the PRUSS > + * INTC instance > + */ > +#define MAX_NUM_HOST_IRQS 8 > + > +/* minimum starting host interrupt number for MPU */ > +#define MIN_PRU_HOST_INT 2 > + > +/* maximum number of system events */ > +#define MAX_PRU_SYS_EVENTS 64 > + > +/* PRU_ICSS_INTC registers */ > +#define PRU_INTC_REVID 0x0000 > +#define PRU_INTC_CR 0x0004 > +#define PRU_INTC_GER 0x0010 > +#define PRU_INTC_GNLR 0x001c > +#define PRU_INTC_SISR 0x0020 > +#define PRU_INTC_SICR 0x0024 > +#define PRU_INTC_EISR 0x0028 > +#define PRU_INTC_EICR 0x002c > +#define PRU_INTC_HIEISR 0x0034 > +#define PRU_INTC_HIDISR 0x0038 > +#define PRU_INTC_GPIR 0x0080 > +#define PRU_INTC_SRSR0 0x0200 > +#define PRU_INTC_SRSR1 0x0204 > +#define PRU_INTC_SECR0 0x0280 > +#define PRU_INTC_SECR1 0x0284 > +#define PRU_INTC_ESR0 0x0300 > +#define PRU_INTC_ESR1 0x0304 > +#define PRU_INTC_ECR0 0x0380 > +#define PRU_INTC_ECR1 0x0384 > +#define PRU_INTC_CMR(x) (0x0400 + (x) * 4) > +#define PRU_INTC_HMR(x) (0x0800 + (x) * 4) > +#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4) > +#define PRU_INTC_SIPR0 0x0d00 > +#define PRU_INTC_SIPR1 0x0d04 > +#define PRU_INTC_SITR0 0x0d80 > +#define PRU_INTC_SITR1 0x0d84 > +#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) > +#define PRU_INTC_HIER 0x1500 > + > +/* HIPIR register bit-fields */ > +#define INTC_HIPIR_NONE_HINT 0x80000000 Unused macro. See below. > + > +/** > + * struct pruss_intc - PRUSS interrupt controller structure > + * @irqs: kernel irq numbers corresponding to PRUSS host interrupts > + * @base: base virtual address of INTC register space > + * @irqchip: irq chip for this interrupt controller > + * @domain: irq domain for this interrupt controller > + * @lock: mutex to serialize access to INTC > + * @host_mask: indicate which HOST IRQs are enabled > + */ > +struct pruss_intc { > + unsigned int irqs[MAX_NUM_HOST_IRQS]; > + void __iomem *base; > + struct irq_chip *irqchip; > + struct irq_domain *domain; > + struct mutex lock; /* PRUSS INTC lock */ > + u32 host_mask; > +}; > + > +static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg) > +{ > + return readl_relaxed(intc->base + reg); > +} > + > +static inline void pruss_intc_write_reg(struct pruss_intc *intc, > + unsigned int reg, u32 val) > +{ > + writel_relaxed(val, intc->base + reg); > +} > + > +static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, > + unsigned int sysevent) > +{ > + if (!intc) > + return -EINVAL; > + > + if (sysevent >= MAX_PRU_SYS_EVENTS) > + return -EINVAL; > + > + pruss_intc_write_reg(intc, reg, sysevent); > + > + return 0; > +} > + > +static void pruss_intc_init(struct pruss_intc *intc) > +{ > + int i; > + > + /* configure polarity to active high for all system interrupts */ > + pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff); > + pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff); > + > + /* configure type to pulse interrupt for all system interrupts */ > + pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0); > + pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0); > + > + /* clear all 16 interrupt channel map registers */ > + for (i = 0; i < 16; i++) > + pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0); > + > + /* clear all 3 host interrupt map registers */ > + for (i = 0; i < 3; i++) > + pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0); > +} > + > +static void pruss_intc_irq_ack(struct irq_data *data) > +{ > + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); > + unsigned int hwirq = data->hwirq; > + > + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); > +} > + > +static void pruss_intc_irq_mask(struct irq_data *data) > +{ > + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); > + unsigned int hwirq = data->hwirq; > + > + pruss_intc_check_write(intc, PRU_INTC_EICR, hwirq); > +} > + > +static void pruss_intc_irq_unmask(struct irq_data *data) > +{ > + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); > + unsigned int hwirq = data->hwirq; > + > + pruss_intc_check_write(intc, PRU_INTC_EISR, hwirq); > +} > + > +static int pruss_intc_irq_retrigger(struct irq_data *data) > +{ > + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); > + unsigned int hwirq = data->hwirq; > + > + return pruss_intc_check_write(intc, PRU_INTC_SISR, hwirq); > +} > + > +static int pruss_intc_irq_reqres(struct irq_data *data) > +{ > + if (!try_module_get(THIS_MODULE)) > + return -ENODEV; > + > + return 0; > +} > + > +static void pruss_intc_irq_relres(struct irq_data *data) > +{ > + module_put(THIS_MODULE); > +} > + > +static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq, > + irq_hw_number_t hw) > +{ > + struct pruss_intc *intc = d->host_data; > + > + irq_set_chip_data(virq, intc); > + irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq); > + > + return 0; > +} > + > +static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq) > +{ > + irq_set_chip_and_handler(virq, NULL, NULL); > + irq_set_chip_data(virq, NULL); > +} > + > +static const struct irq_domain_ops pruss_intc_irq_domain_ops = { > + .xlate = irq_domain_xlate_onecell, > + .map = pruss_intc_irq_domain_map, > + .unmap = pruss_intc_irq_domain_unmap, > +}; > + > +static void pruss_intc_irq_handler(struct irq_desc *desc) > +{ > + unsigned int irq = irq_desc_get_irq(desc); > + struct irq_chip *chip = irq_desc_get_chip(desc); > + struct pruss_intc *intc = irq_get_handler_data(irq); > + u32 hipir; > + unsigned int virq; > + int i, hwirq; > + > + chained_irq_enter(chip, desc); > + > + /* find our host irq number */ > + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) > + if (intc->irqs[i] == irq) > + break; > + if (i == MAX_NUM_HOST_IRQS) > + goto err; > + > + i += MIN_PRU_HOST_INT; > + > + /* get highest priority pending PRUSS system event */ > + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); > + while (!(hipir & BIT(31))) { Is BIT(31) here supposed to be INTC_HIPIR_NONE_HINT? > + hwirq = hipir & GENMASK(9, 0); > + virq = irq_linear_revmap(intc->domain, hwirq); > + > + /* > + * NOTE: manually ACK any system events that do not have a > + * handler mapped yet > + */ > + if (unlikely(!virq)) > + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); > + else > + generic_handle_irq(virq); > + > + /* get next system event */ > + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); > + } > +err: > + chained_irq_exit(chip, desc); > +} > + > +static int pruss_intc_probe(struct platform_device *pdev) > +{ > + static const char * const irq_names[] = { > + "host0", "host1", "host2", "host3", > + "host4", "host5", "host6", "host7", }; > + struct device *dev = &pdev->dev; > + struct pruss_intc *intc; > + struct resource *res; > + struct irq_chip *irqchip; > + int i, irq; > + > + intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); > + if (!intc) > + return -ENOMEM; > + platform_set_drvdata(pdev, intc); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + intc->base = devm_ioremap_resource(dev, res); > + if (IS_ERR(intc->base)) { > + dev_err(dev, "failed to parse and map intc memory resource\n"); > + return PTR_ERR(intc->base); > + } > + > + dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start, > + (size_t)resource_size(res), intc->base); > + > + mutex_init(&intc->lock); > + > + pruss_intc_init(intc); > + > + irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); > + if (!irqchip) > + return -ENOMEM; > + > + irqchip->irq_ack = pruss_intc_irq_ack; > + irqchip->irq_mask = pruss_intc_irq_mask; > + irqchip->irq_unmask = pruss_intc_irq_unmask; > + irqchip->irq_retrigger = pruss_intc_irq_retrigger; > + irqchip->irq_request_resources = pruss_intc_irq_reqres; > + irqchip->irq_release_resources = pruss_intc_irq_relres; > + irqchip->name = dev_name(dev); Should we also set `irqchip->parent_device = dev;` here? I tried it and had to add pm runtime stuff as well, otherwise requesting irqs would fail. > + intc->irqchip = irqchip; > + > + /* always 64 events */ > + intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS, > + &pruss_intc_irq_domain_ops, intc); > + if (!intc->domain) > + return -ENOMEM; > + > + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { > + irq = platform_get_irq_byname(pdev, irq_names[i]); > + if (irq < 0) { > + dev_err(dev->parent, "platform_get_irq_byname failed for %s : %d\n", Why dev->parent instead of just dev? > + irq_names[i], irq); > + goto fail_irq; > + } > + > + intc->irqs[i] = irq; > + irq_set_handler_data(irq, intc); > + irq_set_chained_handler(irq, pruss_intc_irq_handler); > + } > + > + return 0; > + > +fail_irq: > + while (--i >= 0) { > + if (intc->irqs[i]) > + irq_set_chained_handler_and_data(intc->irqs[i], NULL, > + NULL); > + } > + irq_domain_remove(intc->domain); > + return irq; > +} > + > +static int pruss_intc_remove(struct platform_device *pdev) > +{ > + struct pruss_intc *intc = platform_get_drvdata(pdev); > + unsigned int hwirq; > + int i; > + > + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { > + if (intc->irqs[i]) > + irq_set_chained_handler_and_data(intc->irqs[i], NULL, > + NULL); > + } > + > + if (intc->domain) { Is it actuall possible for intc->domain to be NULL here? > + for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) > + irq_dispose_mapping(irq_find_mapping(intc->domain, > + hwirq)); > + irq_domain_remove(intc->domain); > + } > + > + return 0; > +} > + > +static const struct of_device_id pruss_intc_of_match[] = { > + { .compatible = "ti,pruss-intc", }, > + { /* sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, pruss_intc_of_match); > + > +static struct platform_driver pruss_intc_driver = { > + .driver = { > + .name = "pruss-intc", > + .of_match_table = pruss_intc_of_match, > + }, > + .probe = pruss_intc_probe, > + .remove = pruss_intc_remove, > +}; > +module_platform_driver(pruss_intc_driver); > + > +MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>"); > +MODULE_AUTHOR("Suman Anna <s-anna@ti.com>"); > +MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver"); > +MODULE_LICENSE("GPL v2"); >
Hi David, On 7/11/19 11:45 AM, David Lechner wrote: > On 7/7/19 10:52 PM, Suman Anna wrote: >> From: "Andrew F. Davis" <afd@ti.com> >> >> The Programmable Real-Time Unit Subsystem (PRUSS) contains a local >> interrupt controller (INTC) that can handle various system input events >> and post interrupts back to the device-level initiators. The INTC can >> support upto 64 input events with individual control configuration and >> hardware prioritization. These events are mapped onto 10 output interrupt >> lines through two levels of many-to-one mapping support. Different >> interrupt lines are routed to the individual PRU cores or to the host >> CPU, or to other devices on the SoC. Some of these events are sourced >> from peripherals or other sub-modules within that PRUSS, while a few >> others are sourced from SoC-level peripherals/devices. >> >> The PRUSS INTC platform driver manages this PRUSS interrupt controller >> and implements an irqchip driver to provide a Linux standard way for >> the PRU client users to enable/disable/ack/re-trigger a PRUSS system >> event. The system events to interrupt channels and host interrupts >> relies on the mapping configuration provided either through the PRU >> firmware blob or via the PRU application's device tree node. The >> mappings will be programmed during the boot/shutdown of a PRU core. >> >> The PRUSS INTC module is reference counted during the interrupt >> setup phase through the irqchip's irq_request_resources() and >> irq_release_resources() ops. This restricts the module from being >> removed as long as there are active interrupt users. >> >> The driver currently supports and can be built for OMAP architecture >> based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based >> 66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs. >> All of these SoCs support 64 system events, 10 interrupt channels and >> 10 output interrupt lines per PRUSS INTC with a few SoC integration >> differences. >> >> NOTE: >> Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that >> enables multiple external events to be routed to a specific number >> of input interrupt events. Any non-default external interrupt event >> directed towards PRUSS needs this crossbar to be setup properly. > > The all of the explanations above are very helpful. Great work. > >> >> Signed-off-by: Andrew F. Davis <afd@ti.com> >> Signed-off-by: Suman Anna <s-anna@ti.com> >> Signed-off-by: Roger Quadros <rogerq@ti.com> >> --- >> Prior version: https://patchwork.kernel.org/patch/10795761/ >> >> drivers/irqchip/Kconfig | 10 + >> drivers/irqchip/Makefile | 1 + >> drivers/irqchip/irq-pruss-intc.c | 352 +++++++++++++++++++++++++++++++ >> 3 files changed, 363 insertions(+) >> create mode 100644 drivers/irqchip/irq-pruss-intc.c >> >> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig >> index 659c5e0fb835..b0a9479d527c 100644 >> --- a/drivers/irqchip/Kconfig >> +++ b/drivers/irqchip/Kconfig >> @@ -447,6 +447,16 @@ config TI_SCI_INTA_IRQCHIP >> If you wish to use interrupt aggregator irq resources managed >> by the >> TI System Controller, say Y here. Otherwise, say N. >> +config TI_PRUSS_INTC >> + tristate "TI PRU-ICSS Interrupt Controller" >> + depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX >> || ARCH_KEYSTONE >> + select IRQ_DOMAIN >> + help >> + This enables support for the PRU-ICSS Local Interrupt Controller >> + present within a PRU-ICSS subsystem present on various TI SoCs. >> + The PRUSS INTC enables various interrupts to be routed to >> multiple >> + different processors within the SoC. >> + >> endmenu >> config SIFIVE_PLIC >> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile >> index 606a003a0000..717f1d49e549 100644 >> --- a/drivers/irqchip/Makefile >> +++ b/drivers/irqchip/Makefile >> @@ -100,3 +100,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o >> obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o >> obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o >> obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o >> +obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o >> diff --git a/drivers/irqchip/irq-pruss-intc.c >> b/drivers/irqchip/irq-pruss-intc.c >> new file mode 100644 >> index 000000000000..d62186ad1be4 >> --- /dev/null >> +++ b/drivers/irqchip/irq-pruss-intc.c >> @@ -0,0 +1,352 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PRU-ICSS INTC IRQChip driver for various TI SoCs >> + * >> + * Copyright (C) 2016-2019 Texas Instruments Incorporated - >> http://www.ti.com/ >> + * Andrew F. Davis <afd@ti.com> >> + * Suman Anna <s-anna@ti.com> >> + */ >> + >> +#include <linux/irq.h> >> +#include <linux/irqchip/chained_irq.h> >> +#include <linux/irqdomain.h> >> +#include <linux/module.h> >> +#include <linux/of_device.h> >> +#include <linux/platform_device.h> >> + >> +/* >> + * Number of host interrupts reaching the main MPU sub-system. Note >> that this >> + * is not the same as the total number of host interrupts supported >> by the PRUSS >> + * INTC instance >> + */ >> +#define MAX_NUM_HOST_IRQS 8 >> + >> +/* minimum starting host interrupt number for MPU */ >> +#define MIN_PRU_HOST_INT 2 >> + >> +/* maximum number of system events */ >> +#define MAX_PRU_SYS_EVENTS 64 >> + >> +/* PRU_ICSS_INTC registers */ >> +#define PRU_INTC_REVID 0x0000 >> +#define PRU_INTC_CR 0x0004 >> +#define PRU_INTC_GER 0x0010 >> +#define PRU_INTC_GNLR 0x001c >> +#define PRU_INTC_SISR 0x0020 >> +#define PRU_INTC_SICR 0x0024 >> +#define PRU_INTC_EISR 0x0028 >> +#define PRU_INTC_EICR 0x002c >> +#define PRU_INTC_HIEISR 0x0034 >> +#define PRU_INTC_HIDISR 0x0038 >> +#define PRU_INTC_GPIR 0x0080 >> +#define PRU_INTC_SRSR0 0x0200 >> +#define PRU_INTC_SRSR1 0x0204 >> +#define PRU_INTC_SECR0 0x0280 >> +#define PRU_INTC_SECR1 0x0284 >> +#define PRU_INTC_ESR0 0x0300 >> +#define PRU_INTC_ESR1 0x0304 >> +#define PRU_INTC_ECR0 0x0380 >> +#define PRU_INTC_ECR1 0x0384 >> +#define PRU_INTC_CMR(x) (0x0400 + (x) * 4) >> +#define PRU_INTC_HMR(x) (0x0800 + (x) * 4) >> +#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4) >> +#define PRU_INTC_SIPR0 0x0d00 >> +#define PRU_INTC_SIPR1 0x0d04 >> +#define PRU_INTC_SITR0 0x0d80 >> +#define PRU_INTC_SITR1 0x0d84 >> +#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) >> +#define PRU_INTC_HIER 0x1500 >> + >> +/* HIPIR register bit-fields */ >> +#define INTC_HIPIR_NONE_HINT 0x80000000 > > Unused macro. See below. Will use the macro in the code. > >> + >> +/** >> + * struct pruss_intc - PRUSS interrupt controller structure >> + * @irqs: kernel irq numbers corresponding to PRUSS host interrupts >> + * @base: base virtual address of INTC register space >> + * @irqchip: irq chip for this interrupt controller >> + * @domain: irq domain for this interrupt controller >> + * @lock: mutex to serialize access to INTC >> + * @host_mask: indicate which HOST IRQs are enabled >> + */ >> +struct pruss_intc { >> + unsigned int irqs[MAX_NUM_HOST_IRQS]; >> + void __iomem *base; >> + struct irq_chip *irqchip; >> + struct irq_domain *domain; >> + struct mutex lock; /* PRUSS INTC lock */ >> + u32 host_mask; This is also unused in this patch, will move this to patch 4. >> +}; >> + >> +static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, >> unsigned int reg) >> +{ >> + return readl_relaxed(intc->base + reg); >> +} >> + >> +static inline void pruss_intc_write_reg(struct pruss_intc *intc, >> + unsigned int reg, u32 val) >> +{ >> + writel_relaxed(val, intc->base + reg); >> +} >> + >> +static int pruss_intc_check_write(struct pruss_intc *intc, unsigned >> int reg, >> + unsigned int sysevent) >> +{ >> + if (!intc) >> + return -EINVAL; >> + >> + if (sysevent >= MAX_PRU_SYS_EVENTS) >> + return -EINVAL; >> + >> + pruss_intc_write_reg(intc, reg, sysevent); >> + >> + return 0; >> +} >> + >> +static void pruss_intc_init(struct pruss_intc *intc) >> +{ >> + int i; >> + >> + /* configure polarity to active high for all system interrupts */ >> + pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff); >> + pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff); >> + >> + /* configure type to pulse interrupt for all system interrupts */ >> + pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0); >> + pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0); >> + >> + /* clear all 16 interrupt channel map registers */ >> + for (i = 0; i < 16; i++) >> + pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0); >> + >> + /* clear all 3 host interrupt map registers */ >> + for (i = 0; i < 3; i++) >> + pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0); >> +} >> + >> +static void pruss_intc_irq_ack(struct irq_data *data) >> +{ >> + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); >> + unsigned int hwirq = data->hwirq; >> + >> + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); >> +} >> + >> +static void pruss_intc_irq_mask(struct irq_data *data) >> +{ >> + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); >> + unsigned int hwirq = data->hwirq; >> + >> + pruss_intc_check_write(intc, PRU_INTC_EICR, hwirq); >> +} >> + >> +static void pruss_intc_irq_unmask(struct irq_data *data) >> +{ >> + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); >> + unsigned int hwirq = data->hwirq; >> + >> + pruss_intc_check_write(intc, PRU_INTC_EISR, hwirq); >> +} >> + >> +static int pruss_intc_irq_retrigger(struct irq_data *data) >> +{ >> + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); >> + unsigned int hwirq = data->hwirq; >> + >> + return pruss_intc_check_write(intc, PRU_INTC_SISR, hwirq); >> +} >> + >> +static int pruss_intc_irq_reqres(struct irq_data *data) >> +{ >> + if (!try_module_get(THIS_MODULE)) >> + return -ENODEV; >> + >> + return 0; >> +} >> + >> +static void pruss_intc_irq_relres(struct irq_data *data) >> +{ >> + module_put(THIS_MODULE); >> +} >> + >> +static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned >> int virq, >> + irq_hw_number_t hw) >> +{ >> + struct pruss_intc *intc = d->host_data; >> + >> + irq_set_chip_data(virq, intc); >> + irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq); >> + >> + return 0; >> +} >> + >> +static void pruss_intc_irq_domain_unmap(struct irq_domain *d, >> unsigned int virq) >> +{ >> + irq_set_chip_and_handler(virq, NULL, NULL); >> + irq_set_chip_data(virq, NULL); >> +} >> + >> +static const struct irq_domain_ops pruss_intc_irq_domain_ops = { >> + .xlate = irq_domain_xlate_onecell, >> + .map = pruss_intc_irq_domain_map, >> + .unmap = pruss_intc_irq_domain_unmap, >> +}; >> + >> +static void pruss_intc_irq_handler(struct irq_desc *desc) >> +{ >> + unsigned int irq = irq_desc_get_irq(desc); >> + struct irq_chip *chip = irq_desc_get_chip(desc); >> + struct pruss_intc *intc = irq_get_handler_data(irq); >> + u32 hipir; >> + unsigned int virq; >> + int i, hwirq; >> + >> + chained_irq_enter(chip, desc); >> + >> + /* find our host irq number */ >> + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) >> + if (intc->irqs[i] == irq) >> + break; >> + if (i == MAX_NUM_HOST_IRQS) >> + goto err; >> + >> + i += MIN_PRU_HOST_INT; >> + >> + /* get highest priority pending PRUSS system event */ >> + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); >> + while (!(hipir & BIT(31))) { > > Is BIT(31) here supposed to be INTC_HIPIR_NONE_HINT? Yes, will replace BIT(31) with the macro. > >> + hwirq = hipir & GENMASK(9, 0); >> + virq = irq_linear_revmap(intc->domain, hwirq); >> + >> + /* >> + * NOTE: manually ACK any system events that do not have a >> + * handler mapped yet >> + */ >> + if (unlikely(!virq)) >> + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); >> + else >> + generic_handle_irq(virq); >> + >> + /* get next system event */ >> + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); >> + } >> +err: >> + chained_irq_exit(chip, desc); >> +} >> + >> +static int pruss_intc_probe(struct platform_device *pdev) >> +{ >> + static const char * const irq_names[] = { >> + "host0", "host1", "host2", "host3", >> + "host4", "host5", "host6", "host7", }; >> + struct device *dev = &pdev->dev; >> + struct pruss_intc *intc; >> + struct resource *res; >> + struct irq_chip *irqchip; >> + int i, irq; >> + >> + intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); >> + if (!intc) >> + return -ENOMEM; >> + platform_set_drvdata(pdev, intc); >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + intc->base = devm_ioremap_resource(dev, res); >> + if (IS_ERR(intc->base)) { >> + dev_err(dev, "failed to parse and map intc memory resource\n"); >> + return PTR_ERR(intc->base); >> + } >> + >> + dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start, >> + (size_t)resource_size(res), intc->base); >> + >> + mutex_init(&intc->lock); >> + >> + pruss_intc_init(intc); >> + >> + irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); >> + if (!irqchip) >> + return -ENOMEM; >> + >> + irqchip->irq_ack = pruss_intc_irq_ack; >> + irqchip->irq_mask = pruss_intc_irq_mask; >> + irqchip->irq_unmask = pruss_intc_irq_unmask; >> + irqchip->irq_retrigger = pruss_intc_irq_retrigger; >> + irqchip->irq_request_resources = pruss_intc_irq_reqres; >> + irqchip->irq_release_resources = pruss_intc_irq_relres; >> + irqchip->name = dev_name(dev); > > Should we also set `irqchip->parent_device = dev;` here? > > I tried it and had to add pm runtime stuff as well, otherwise > requesting irqs would fail. I haven't seen any during my local testing. What sort of failure are you seeing? The clocking for the overall PRUSS module will be handled in either the ti-sysc driver for OMAP SoCs or in the pruss platform driver. > >> + intc->irqchip = irqchip; >> + >> + /* always 64 events */ >> + intc->domain = irq_domain_add_linear(dev->of_node, >> MAX_PRU_SYS_EVENTS, >> + &pruss_intc_irq_domain_ops, intc); >> + if (!intc->domain) >> + return -ENOMEM; >> + >> + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { >> + irq = platform_get_irq_byname(pdev, irq_names[i]); >> + if (irq < 0) { >> + dev_err(dev->parent, "platform_get_irq_byname failed for >> %s : %d\n", > > Why dev->parent instead of just dev? Yeah, will fix this. It is a vestige from previous code where we were actually parsing the interrupts from the PRUSS node instead of the PRUSS INTC node. > >> + irq_names[i], irq); >> + goto fail_irq; >> + } >> + >> + intc->irqs[i] = irq; >> + irq_set_handler_data(irq, intc); >> + irq_set_chained_handler(irq, pruss_intc_irq_handler); >> + } >> + >> + return 0; >> + >> +fail_irq: >> + while (--i >= 0) { >> + if (intc->irqs[i]) >> + irq_set_chained_handler_and_data(intc->irqs[i], NULL, >> + NULL); >> + } >> + irq_domain_remove(intc->domain); >> + return irq; >> +} >> + >> +static int pruss_intc_remove(struct platform_device *pdev) >> +{ >> + struct pruss_intc *intc = platform_get_drvdata(pdev); >> + unsigned int hwirq; >> + int i; >> + >> + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { >> + if (intc->irqs[i]) >> + irq_set_chained_handler_and_data(intc->irqs[i], NULL, >> + NULL); >> + } >> + >> + if (intc->domain) { > > Is it actuall possible for intc->domain to be NULL here? Nope, will remove it. Thank you for all the review comments. regards Suman > >> + for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) >> + irq_dispose_mapping(irq_find_mapping(intc->domain, >> + hwirq)); >> + irq_domain_remove(intc->domain); >> + } >> + >> + return 0; >> +} >> + >> +static const struct of_device_id pruss_intc_of_match[] = { >> + { .compatible = "ti,pruss-intc", }, >> + { /* sentinel */ }, >> +}; >> +MODULE_DEVICE_TABLE(of, pruss_intc_of_match); >> + >> +static struct platform_driver pruss_intc_driver = { >> + .driver = { >> + .name = "pruss-intc", >> + .of_match_table = pruss_intc_of_match, >> + }, >> + .probe = pruss_intc_probe, >> + .remove = pruss_intc_remove, >> +}; >> +module_platform_driver(pruss_intc_driver); >> + >> +MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>"); >> +MODULE_AUTHOR("Suman Anna <s-anna@ti.com>"); >> +MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver"); >> +MODULE_LICENSE("GPL v2"); >> >
Hi David, On 7/10/19 10:10 PM, David Lechner wrote: > On 7/7/19 10:52 PM, Suman Anna wrote: >> The PRUSS INTC receives a number of system input interrupt source events >> and supports individual control configuration and hardware >> prioritization. >> These input events can be mapped to some output host interrupts through 2 >> levels of many-to-one mapping i.e. events to channel mapping and channels >> to host interrupts. >> >> This mapping information is provided through the PRU firmware that is >> loaded onto a PRU core/s or through the device tree node of the PRU > Thanks for the thorough review and alternate solutions/suggestions. > What will the device tree bindings for this look like? They would be as in the below patch you already figured. > > Looking back at Rob's comment on the initial series [1], I still think > that increasing the #interrupt-cells sounds like a reasonable solution. > > [1]: https://patchwork.kernel.org/patch/10697705/#22375155 So, there are couple of reasons why I did not use an extended #interrupt-cells: 1. There is only one irq descriptor associated with each event, and the usage of events is typically per application. And the descriptor mapping is done once. We can have two different applications use the same event with different mappings. So we want this programming done at application's usage of PRU (so done when a consumer driver acquires a PRU processor(s) which are treated as an exclusive resource). All the different application properties that you saw in [1] are configured at the time of acquiring a PRU and reset when they release a PRU. 2. The configuration is performed by Linux for all host interrupts and channels, and this was primarily done to save the very limited IRAM space for those needed by the PRUs. From firmware's point of view, this was offloaded to the ARM OS driver/infrastructure, but in general it is a design by contract between a PRU client driver and its firmware. Also, the DT binding semantics using interrupts property and request_irq() typically limits these to interrupts only being requested by MPU, and so will leave out those needed by PRUs. > > > >> application. The mapping is configured by the PRU remoteproc driver, and >> is setup before the PRU core is started and cleaned up after the PRU core >> is stopped. This event mapping configuration logic is optimized to >> program >> the Channel Map Registers (CMRx) and Host-Interrupt Map Registers (HMRx) >> only when a new program is being loaded/started and simply disables the >> same events and interrupt channels without zeroing out the corresponding >> map registers when stopping a PRU. >> >> Add two helper functions: pruss_intc_configure() & >> pruss_intc_unconfigure() >> that the PRU remoteproc driver can use to configure the PRUSS INTC. >> >> Signed-off-by: Suman Anna <s-anna@ti.com> >> Signed-off-by: Andrew F. Davis <afd@ti.com> >> Signed-off-by: Roger Quadros <rogerq@ti.com> >> --- >> drivers/irqchip/irq-pruss-intc.c | 258 ++++++++++++++++++++++++- >> include/linux/irqchip/irq-pruss-intc.h | 33 ++++ >> 2 files changed, 289 insertions(+), 2 deletions(-) >> create mode 100644 include/linux/irqchip/irq-pruss-intc.h >> >> diff --git a/drivers/irqchip/irq-pruss-intc.c >> b/drivers/irqchip/irq-pruss-intc.c >> index 142d01b434e0..8118c2a2ac43 100644 >> --- a/drivers/irqchip/irq-pruss-intc.c >> +++ b/drivers/irqchip/irq-pruss-intc.c >> @@ -9,6 +9,7 @@ >> #include <linux/irq.h> >> #include <linux/irqchip/chained_irq.h> >> +#include <linux/irqchip/irq-pruss-intc.h> >> #include <linux/irqdomain.h> >> #include <linux/module.h> >> #include <linux/of_device.h> >> @@ -24,8 +25,8 @@ >> /* minimum starting host interrupt number for MPU */ >> #define MIN_PRU_HOST_INT 2 >> -/* maximum number of system events */ >> -#define MAX_PRU_SYS_EVENTS 64 >> +/* maximum number of host interrupts */ >> +#define MAX_PRU_HOST_INT 10 >> /* PRU_ICSS_INTC registers */ >> #define PRU_INTC_REVID 0x0000 >> @@ -57,15 +58,29 @@ >> #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) >> #define PRU_INTC_HIER 0x1500 >> +/* CMR register bit-field macros */ >> +#define CMR_EVT_MAP_MASK 0xf >> +#define CMR_EVT_MAP_BITS 8 >> +#define CMR_EVT_PER_REG 4 >> + >> +/* HMR register bit-field macros */ >> +#define HMR_CH_MAP_MASK 0xf >> +#define HMR_CH_MAP_BITS 8 >> +#define HMR_CH_PER_REG 4 >> + >> /* HIPIR register bit-fields */ >> #define INTC_HIPIR_NONE_HINT 0x80000000 >> +/* use -1 to mark unassigned events and channels */ >> +#define FREE -1 > > It could be helpful to have this macro in the public header. Yes, I can rename it and move it, and I can reuse it in the parsing logic within the PRU remoteproc driver as well. > >> + >> /** >> * struct pruss_intc - PRUSS interrupt controller structure >> * @irqs: kernel irq numbers corresponding to PRUSS host interrupts >> * @base: base virtual address of INTC register space >> * @irqchip: irq chip for this interrupt controller >> * @domain: irq domain for this interrupt controller >> + * @config_map: stored INTC configuration mapping data >> * @lock: mutex to serialize access to INTC >> * @host_mask: indicate which HOST IRQs are enabled >> * @shared_intr: bit-map denoting if the MPU host interrupt is shared >> @@ -76,6 +91,7 @@ struct pruss_intc { >> void __iomem *base; >> struct irq_chip *irqchip; >> struct irq_domain *domain; >> + struct pruss_intc_config config_map; >> struct mutex lock; /* PRUSS INTC lock */ >> u32 host_mask; >> u16 shared_intr; >> @@ -107,6 +123,238 @@ static int pruss_intc_check_write(struct >> pruss_intc *intc, unsigned int reg, >> return 0; >> } >> +static struct pruss_intc *to_pruss_intc(struct device *pru_dev) >> +{ >> + struct device_node *np; >> + struct platform_device *pdev; >> + struct device *pruss_dev = pru_dev->parent; >> + struct pruss_intc *intc = ERR_PTR(-ENODEV); >> + >> + np = of_get_child_by_name(pruss_dev->of_node, >> "interrupt-controller"); >> + if (!np) { >> + dev_err(pruss_dev, "pruss does not have an >> interrupt-controller node\n"); >> + return intc; >> + } >> + >> + pdev = of_find_device_by_node(np); >> + if (!pdev) { >> + dev_err(pruss_dev, "no associated platform device\n"); >> + goto out; >> + } >> + >> + intc = platform_get_drvdata(pdev); >> + if (!intc) { >> + dev_err(pruss_dev, "pruss intc device probe failed?\n"); >> + intc = ERR_PTR(-EINVAL); >> + } >> + >> +out: >> + of_node_put(np); >> + return intc; >> +} >> + >> +/** >> + * pruss_intc_configure() - configure the PRUSS INTC >> + * @dev: pru device pointer >> + * @intc_config: PRU core-specific INTC configuration >> + * >> + * Configures the PRUSS INTC with the provided configuration from >> + * a PRU core. Any existing event to channel mappings or channel to >> + * host interrupt mappings are checked to make sure there are no >> + * conflicting configuration between both the PRU cores. The function >> + * is intended to be used only by the PRU remoteproc driver. >> + * >> + * Returns 0 on success, or a suitable error code otherwise >> + */ >> +int pruss_intc_configure(struct device *dev, > > It seems like this would be easier to use if it took an IRQ number > or struct irq_data * as a parameter instead of struct device *. My > line of thinking is that callers of this function will already be > calling some variant of request_irq() so they will already have > this info. It would cut out the pointer acrobatics in to_pruss_intc. These API are actually not seen by PRU client drivers, but is only limited to the PRU remoteproc driver. The INTC configuration is managed per PRU core and in sync with the life-cycle of the PRU load/start and stop. As I mentioned above, we need to manage the configuration for events generating interrupts to non Linux ARM host as well. > > >> + struct pruss_intc_config *intc_config) >> +{ >> + struct pruss_intc *intc; >> + int i, idx, ret; >> + s8 ch, host; >> + u64 sysevt_mask = 0; >> + u32 ch_mask = 0; >> + u32 host_mask = 0; >> + u32 val; >> + >> + intc = to_pruss_intc(dev); >> + if (IS_ERR(intc)) >> + return PTR_ERR(intc); >> + >> + mutex_lock(&intc->lock); >> + >> + /* >> + * configure channel map registers - each register holds map info >> + * for 4 events, with each event occupying the lower nibble in >> + * a register byte address in little-endian fashion >> + */ >> + for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { >> + ch = intc_config->sysev_to_ch[i]; >> + if (ch < 0) >> + continue; >> + >> + /* check if sysevent already assigned */ >> + if (intc->config_map.sysev_to_ch[i] != FREE) { >> + dev_err(dev, "event %d (req. channel %d) already assigned >> to channel %d\n", >> + i, ch, intc->config_map.sysev_to_ch[i]); >> + ret = -EEXIST; >> + goto unlock; > > If we fail here, shouldn't we unwind any previous mappings made? > Otherwise, if we try to map the same event again, it will show as > in use, even though it is not in use. Yeah, I will fix up the unwind logic. I intended for the callers to invoke the unconfigure upon failures, but even that has some unneeded operations, so it is better to unwind the operations here for a cleaner style. > >> + } >> + >> + intc->config_map.sysev_to_ch[i] = ch; >> + >> + idx = i / CMR_EVT_PER_REG; >> + val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)); >> + val &= ~(CMR_EVT_MAP_MASK << >> + ((i % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS)); >> + val |= ch << ((i % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS); >> + pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val); >> + sysevt_mask |= BIT_ULL(i); >> + ch_mask |= BIT(ch); >> + >> + dev_dbg(dev, "SYSEV%d -> CH%d (CMR%d 0x%08x)\n", i, ch, idx, >> + pruss_intc_read_reg(intc, PRU_INTC_CMR(idx))); >> + } >> + >> + /* >> + * set host map registers - each register holds map info for >> + * 4 channels, with each channel occupying the lower nibble in >> + * a register byte address in little-endian fashion >> + */ >> + for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { >> + host = intc_config->ch_to_host[i]; >> + if (host < 0) >> + continue; >> + >> + /* check if channel already assigned */ >> + if (intc->config_map.ch_to_host[i] != FREE) { >> + dev_err(dev, "channel %d (req. intr_no %d) already >> assigned to intr_no %d\n", >> + i, host, intc->config_map.ch_to_host[i]); >> + ret = -EEXIST; >> + goto unlock; > > Same comment about unwinding here and below. Yep, will fix this up as well in the next version. > >> + } >> + >> + /* check if host intr is already in use by other PRU */ > > It seems like there would be use cases where someone might want to map > multiple PRU system events, and therefore multiple channels, to a single > host interrupt. Yes, that is in general supported but for a given PRU. The idea here was to partition the host events separately between two PRUs and this is done to simplify the life-cycle per host event and their mappings between two different PRUs potentially running two different unrelated co-operative applications. > >> + if (intc->host_mask & (1U << host)) { >> + dev_err(dev, "%s: host intr %d already in use\n", >> + __func__, host); >> + ret = -EEXIST; >> + goto unlock; >> + } >> + > > --snip-- > >> diff --git a/include/linux/irqchip/irq-pruss-intc.h >> b/include/linux/irqchip/irq-pruss-intc.h >> new file mode 100644 >> index 000000000000..f1f1bb150100 >> --- /dev/null >> +++ b/include/linux/irqchip/irq-pruss-intc.h >> @@ -0,0 +1,33 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * PRU-ICSS sub-system private interfaces >> + * >> + * Copyright (C) 2019 Texas Instruments Incorporated - >> http://www.ti.com/ >> + * Suman Anna <s-anna@ti.com> >> + */ >> + >> +#ifndef __LINUX_IRQ_PRUSS_INTC_H >> +#define __LINUX_IRQ_PRUSS_INTC_H >> + >> +/* maximum number of system events */ >> +#define MAX_PRU_SYS_EVENTS 64 >> + >> +/* maximum number of interrupt channels */ >> +#define MAX_PRU_CHANNELS 10 >> + >> +/** >> + * struct pruss_intc_config - INTC configuration info >> + * @sysev_to_ch: system events to channel mapping information >> + * @ch_to_host: interrupt channel to host interrupt information >> + */ >> +struct pruss_intc_config { >> + s8 sysev_to_ch[MAX_PRU_SYS_EVENTS]; >> + s8 ch_to_host[MAX_PRU_CHANNELS]; >> +}; >> + >> +int pruss_intc_configure(struct device *dev, >> + struct pruss_intc_config *intc_config); >> +int pruss_intc_unconfigure(struct device *dev, >> + struct pruss_intc_config *intc_config); >> + >> +#endif /* __LINUX_IRQ_PRUSS_INTC_H */ >> > > FYI, on AM18xx, events 0 to 31 can be muxed via CFGCHIP3[3].PRUSSEVTSEL > so an additional bit of information will be needed in this struct for > the mux selection. I don't see a probably with adding that later though. Yeah, there are different input pinmux'ing options controlling different number of input events on different SoCs. On AM18xx it is a SoC-level CHIPCFG register, and on other SoCs, it is a PRUSS CFG register (Standard mode vs MII mode) both of which are registers outside of the INTC module. I see these again as an application-level configuration, and this is what the last bullet item in the feature list in my cover-letter is about. I did think about adding a separate property to INTC node to configure a default value at INTC probe time, and then allow it to be overwritten as per a PRU application need. The latter is going to be needed anyway, so I dropped the idea of a default configuration, and leave it at POR values. regards Suman
On 7/16/19 12:21 PM, Suman Anna wrote: >>> +static int pruss_intc_probe(struct platform_device *pdev) >>> +{ >>> + static const char * const irq_names[] = { >>> + "host0", "host1", "host2", "host3", >>> + "host4", "host5", "host6", "host7", }; >>> + struct device *dev = &pdev->dev; >>> + struct pruss_intc *intc; >>> + struct resource *res; >>> + struct irq_chip *irqchip; >>> + int i, irq; >>> + >>> + intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); >>> + if (!intc) >>> + return -ENOMEM; >>> + platform_set_drvdata(pdev, intc); >>> + >>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >>> + intc->base = devm_ioremap_resource(dev, res); >>> + if (IS_ERR(intc->base)) { >>> + dev_err(dev, "failed to parse and map intc memory resource\n"); >>> + return PTR_ERR(intc->base); >>> + } >>> + >>> + dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start, >>> + (size_t)resource_size(res), intc->base); >>> + >>> + mutex_init(&intc->lock); >>> + >>> + pruss_intc_init(intc); >>> + >>> + irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); >>> + if (!irqchip) >>> + return -ENOMEM; >>> + >>> + irqchip->irq_ack = pruss_intc_irq_ack; >>> + irqchip->irq_mask = pruss_intc_irq_mask; >>> + irqchip->irq_unmask = pruss_intc_irq_unmask; >>> + irqchip->irq_retrigger = pruss_intc_irq_retrigger; >>> + irqchip->irq_request_resources = pruss_intc_irq_reqres; >>> + irqchip->irq_release_resources = pruss_intc_irq_relres; >>> + irqchip->name = dev_name(dev); >> >> Should we also set `irqchip->parent_device = dev;` here? >> >> I tried it and had to add pm runtime stuff as well, otherwise >> requesting irqs would fail. > > I haven't seen any during my local testing. What sort of failure are you > seeing? > > The clocking for the overall PRUSS module will be handled in either the > ti-sysc driver for OMAP SoCs or in the pruss platform driver. > I was getting -EACCESS bubbling up from rpm_resume() in drivers/base/ power/runtime.c. It was probably a mix of how I set up the device tree and the dummy PRUSS bus driver I made. I'm sure it will be fine with a proper PRUSS platform driver.
On 7/16/19 6:29 PM, Suman Anna wrote: > Hi David, > > On 7/10/19 10:10 PM, David Lechner wrote: >> On 7/7/19 10:52 PM, Suman Anna wrote: >>> The PRUSS INTC receives a number of system input interrupt source events >>> and supports individual control configuration and hardware >>> prioritization. >>> These input events can be mapped to some output host interrupts through 2 >>> levels of many-to-one mapping i.e. events to channel mapping and channels >>> to host interrupts. >>> >>> This mapping information is provided through the PRU firmware that is >>> loaded onto a PRU core/s or through the device tree node of the PRU >> > > Thanks for the thorough review and alternate solutions/suggestions. > >> What will the device tree bindings for this look like? > > They would be as in the below patch you already figured. Ah, makes sense now: the mapping is defined in the remoteproc node rather than in the interrupt controller node. > >> >> Looking back at Rob's comment on the initial series [1], I still think >> that increasing the #interrupt-cells sounds like a reasonable solution. >> >> [1]: https://patchwork.kernel.org/patch/10697705/#22375155 > > So, there are couple of reasons why I did not use an extended > #interrupt-cells: > > 1. There is only one irq descriptor associated with each event, and the > usage of events is typically per application. And the descriptor mapping > is done once. We can have two different applications use the same event > with different mappings. So we want this programming done at > application's usage of PRU (so done when a consumer driver acquires a > PRU processor(s) which are treated as an exclusive resource). All the > different application properties that you saw in [1] are configured at > the time of acquiring a PRU and reset when they release a PRU. > > 2. The configuration is performed by Linux for all host interrupts and > channels, and this was primarily done to save the very limited IRAM > space for those needed by the PRUs. From firmware's point of view, this > was offloaded to the ARM OS driver/infrastructure, but in general it is > a design by contract between a PRU client driver and its firmware. Also, > the DT binding semantics using interrupts property and request_irq() > typically limits these to interrupts only being requested by MPU, and so > will leave out those needed by PRUs. > Hmm... case 1. is a tricky one indeed. If there are going to be times where an event requires multiple mappings, I agree that this doesn't seem to fit into any existing device tree bindings.
On 7/17/19 12:21 PM, David Lechner wrote: > On 7/16/19 12:21 PM, Suman Anna wrote: >>>> +static int pruss_intc_probe(struct platform_device *pdev) >>>> +{ >>>> + static const char * const irq_names[] = { >>>> + "host0", "host1", "host2", "host3", >>>> + "host4", "host5", "host6", "host7", }; >>>> + struct device *dev = &pdev->dev; >>>> + struct pruss_intc *intc; >>>> + struct resource *res; >>>> + struct irq_chip *irqchip; >>>> + int i, irq; >>>> + >>>> + intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); >>>> + if (!intc) >>>> + return -ENOMEM; >>>> + platform_set_drvdata(pdev, intc); >>>> + >>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >>>> + intc->base = devm_ioremap_resource(dev, res); >>>> + if (IS_ERR(intc->base)) { >>>> + dev_err(dev, "failed to parse and map intc memory >>>> resource\n"); >>>> + return PTR_ERR(intc->base); >>>> + } >>>> + >>>> + dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", >>>> &res->start, >>>> + (size_t)resource_size(res), intc->base); >>>> + >>>> + mutex_init(&intc->lock); >>>> + >>>> + pruss_intc_init(intc); >>>> + >>>> + irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); >>>> + if (!irqchip) >>>> + return -ENOMEM; >>>> + >>>> + irqchip->irq_ack = pruss_intc_irq_ack; >>>> + irqchip->irq_mask = pruss_intc_irq_mask; >>>> + irqchip->irq_unmask = pruss_intc_irq_unmask; >>>> + irqchip->irq_retrigger = pruss_intc_irq_retrigger; >>>> + irqchip->irq_request_resources = pruss_intc_irq_reqres; >>>> + irqchip->irq_release_resources = pruss_intc_irq_relres; >>>> + irqchip->name = dev_name(dev); >>> >>> Should we also set `irqchip->parent_device = dev;` here? >>> >>> I tried it and had to add pm runtime stuff as well, otherwise >>> requesting irqs would fail. >> >> I haven't seen any during my local testing. What sort of failure are you >> seeing? >> >> The clocking for the overall PRUSS module will be handled in either the >> ti-sysc driver for OMAP SoCs or in the pruss platform driver. >> > I was getting -EACCESS bubbling up from rpm_resume() in drivers/base/ > power/runtime.c. It was probably a mix of how I set up the device tree > and the dummy PRUSS bus driver I made. > > I'm sure it will be fine with a proper PRUSS platform driver. Yeah, ok. You just need to have the power-domains property added in the pruss node, and the pm_runtime calls in the pruss platform driver which are missing in Roger's series. I have the following line on my da850 pruss node. power-domains = <&psc0 13>; regards Suman
On 7/17/19 12:57 PM, David Lechner wrote: > On 7/16/19 6:29 PM, Suman Anna wrote: >> Hi David, >> >> On 7/10/19 10:10 PM, David Lechner wrote: >>> On 7/7/19 10:52 PM, Suman Anna wrote: >>>> The PRUSS INTC receives a number of system input interrupt source >>>> events >>>> and supports individual control configuration and hardware >>>> prioritization. >>>> These input events can be mapped to some output host interrupts >>>> through 2 >>>> levels of many-to-one mapping i.e. events to channel mapping and >>>> channels >>>> to host interrupts. >>>> >>>> This mapping information is provided through the PRU firmware that is >>>> loaded onto a PRU core/s or through the device tree node of the PRU >>> >> >> Thanks for the thorough review and alternate solutions/suggestions. >> >>> What will the device tree bindings for this look like? >> >> They would be as in the below patch you already figured. > > Ah, makes sense now: the mapping is defined in the remoteproc node > rather than in the interrupt controller node. Actually in the PRU consumer/application node, but the client driver need not deal with invoking any special API. The functions are called transparently by the PRU remoteproc driver when the PRU client driver acquires a PRU. The 4th cell was used to identify the PRU from the list of prus in the client node. regards Suman > >> >>> >>> Looking back at Rob's comment on the initial series [1], I still think >>> that increasing the #interrupt-cells sounds like a reasonable solution. >>> >>> [1]: https://patchwork.kernel.org/patch/10697705/#22375155 >> >> So, there are couple of reasons why I did not use an extended >> #interrupt-cells: >> >> 1. There is only one irq descriptor associated with each event, and the >> usage of events is typically per application. And the descriptor mapping >> is done once. We can have two different applications use the same event >> with different mappings. So we want this programming done at >> application's usage of PRU (so done when a consumer driver acquires a >> PRU processor(s) which are treated as an exclusive resource). All the >> different application properties that you saw in [1] are configured at >> the time of acquiring a PRU and reset when they release a PRU. >> >> 2. The configuration is performed by Linux for all host interrupts and >> channels, and this was primarily done to save the very limited IRAM >> space for those needed by the PRUs. From firmware's point of view, this >> was offloaded to the ARM OS driver/infrastructure, but in general it is >> a design by contract between a PRU client driver and its firmware. Also, >> the DT binding semantics using interrupts property and request_irq() >> typically limits these to interrupts only being requested by MPU, and so >> will leave out those needed by PRUs. >> > > Hmm... case 1. is a tricky one indeed. If there are going to be times where > an event requires multiple mappings, I agree that this doesn't seem to fit > into any existing device tree bindings. > >
Hi All, The following series adds an IRQChip driver for the local interrupt controller present within a Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) present on a number of TI SoCs including OMAP architecture based AM335x, AM437x, AM57xx SoCs, Keystone 2 architecture based 66AK2G SoCs, Davinci architecture based OMAP-L138/DA850 SoCs and the latest K3 architecture based AM65x and J721E SoCs. This series splits out the INTC portions into a separate stand-alone series from the previous PRUSS support patch series [1] as requested by various maintainers. Patches are on top of latest master. The PRUSS local INTC is a unique interrupt controller designed to map a number of SoC-level device or internal PRUSS interrupt sources into a smaller set of output interrupt lines that are connected to various SoC-level processors like the host ARM, PRU cores themselves and optionally to some DSPs, other PRUSS, DMA controllers etc. The following are some of the features: - Capture of 64 (160 on K3) System Events/input interrupt sources - Multiplexing of these system events onto 10 (20 on K3) output interrupt channels in a many-to-one fashion - Multiplexing of the output interrupt channels onto 10 (20 on K3) host interrupts split between multiple processors. Typical integration connects the first 2 host interrupts to PRU cores, and the next 8 host interrupts to ARM cores. - Independent enable and disable of system events and their mapping onto a channel - Independent enable and disable of host events and the mapping to host events per interrupt channel. - Inherent hardward prioritization of events and channels (lower number indicates higher priority). - Additional input interrupt sources multiplexing using either a SoC-level CFG MMR or PRUSS CFG MMR (support will be added through PRU rproc client bindings). More details can be found in any of the supported SoC TRMs. Eg: Chapter 30.1.6 of AM5728 TRM [2] Changes from previous series include: - Update bindings to move away from SoC-specific compatibles - Use new DT properties to add support for shared and exclusive ARM GIC interrupt lines - Include support for Davinci OMAP-L138 and K3 AM65x & J721E SoCs - Split up the driver patch into granular incremental support patches regards Suman [1] https://patchwork.kernel.org/cover/10795721/ [2] http://www.ti.com/lit/pdf/spruhz6 Andrew F. Davis (2): irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts irqchip/irq-pruss-intc: Add API to trigger a PRU sysevent Suman Anna (4): dt-bindings: irqchip: Add PRUSS interrupt controller bindings irqchip/irq-pruss-intc: Add support for shared and invalid interrupts irqchip/irq-pruss-intc: Add helper functions to configure internal mapping irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs .../interrupt-controller/ti,pruss-intc.txt | 92 +++ drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-pruss-intc.c | 749 ++++++++++++++++++ include/linux/irqchip/irq-pruss-intc.h | 33 + include/linux/pruss_intc.h | 26 + 6 files changed, 911 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt create mode 100644 drivers/irqchip/irq-pruss-intc.c create mode 100644 include/linux/irqchip/irq-pruss-intc.h create mode 100644 include/linux/pruss_intc.h