[v4,0/3] MIPS: ath79: add ag71xx support
mbox series

Message ID 20190519080304.5811-1-o.rempel@pengutronix.de
Headers show
Series
  • MIPS: ath79: add ag71xx support
Related show

Message

Oleksij Rempel May 19, 2019, 8:03 a.m. UTC
2019.04.22 v4:
- DT: define eth and mdio clocks
- ag71xx: remove module parameters
- ag71xx: return proper error value on mdio_read/write
- ag71xx: use proper mdio clock registration
- ag71xx: add ag71xx_dma_wait_stop() for ag71xx_dma_reset()
- ag71xx: remove ag71xx_speed_str()
- ag71xx: use phydev->link/sped/duplex instead of ag-> variants
- ag71xx: use WARN() instead of BUG()
- ag71xx: drop big part of ag71xx_phy_link_adjust()
- ag71xx: drop most of ag71xx_do_ioctl()
- ag71xx: register eth clock
- ag71xx: remove AG71XX_ETH0_NO_MDIO quirk.

2019.04.22 v3:
- ag71xx: use phy_modes() instead of ag71xx_get_phy_if_mode_name()
- ag71xx: remove .ndo_poll_controller support
- ag71xx: unregister_netdev before disconnecting phy.

2019.04.18 v2:
- ag71xx: add list of openwrt authors
- ag71xx: remove redundant PHY_POLL assignment
- ag71xx: use phy_attached_info instead of netif_info
- ag71xx: remove redundant netif_carrier_off() on .stop.
- DT: use "ethernet" instead of "eth"

This patch series provide ethernet support for many Atheros/QCA
MIPS based SoCs.

I reworked ag71xx driver which was previously maintained within OpenWRT
repository. So far, following changes was made to make upstreaming
easier:
- everything what can be some how used in user space was removed. Most
  of it was debug functionality.
- most of deficetree bindings was removed. Not every thing made sense
  and most of it is SoC specific, so it is possible to detect it by
  compatible.
- mac and mdio parts are merged in to one driver. It makes easier to
  maintaine SoC specific quirks.

Oleksij Rempel (3):
  dt-bindings: net: add qca,ar71xx.txt documentation
  MIPS: ath79: ar9331: add Ethernet nodes
  net: ethernet: add ag71xx driver

 .../devicetree/bindings/net/qca,ar71xx.txt    |   45 +
 arch/mips/boot/dts/qca/ar9331.dtsi            |   26 +
 arch/mips/boot/dts/qca/ar9331_dpt_module.dts  |    8 +
 drivers/net/ethernet/atheros/Kconfig          |   11 +-
 drivers/net/ethernet/atheros/Makefile         |    1 +
 drivers/net/ethernet/atheros/ag71xx.c         | 1911 +++++++++++++++++
 6 files changed, 2001 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/net/qca,ar71xx.txt
 create mode 100644 drivers/net/ethernet/atheros/ag71xx.c

Comments

Andrew Lunn May 20, 2019, 12:33 a.m. UTC | #1
Hi Oleksij

> +static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg)
> +{
> +	struct ag71xx *ag = bus->priv;
> +	struct net_device *ndev = ag->ndev;
> +	int err;
> +	int ret;
> +
> +	err = ag71xx_mdio_wait_busy(ag);
> +	if (err)
> +		return err;
> +
> +	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);

It looks like you have not removed this.

> +	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
> +			((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
> +	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
> +
> +	err = ag71xx_mdio_wait_busy(ag);
> +	if (err)
> +		return err;
> +
> +	ret = ag71xx_rr(ag, AG71XX_REG_MII_STATUS);
> +	/*
> +	 * ar9331 doc: bits 31:16 are reserved and must be must be written
> +	 * with zero.
> +	 */
> +	ret &= 0xffff;
> +	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);

Or this.

> +
> +	netif_dbg(ag, link, ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n",
> +		  addr, reg, ret);
> +
> +	return ret;
> +}
> +
> +static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg,
> +				 u16 val)
> +{
> +	struct ag71xx *ag = bus->priv;
> +	struct net_device *ndev = ag->ndev;
> +
> +	netif_dbg(ag, link, ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n",
> +		  addr, reg, val);
> +
> +	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
> +			((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));

addr have the vale 0-31. So a mask of 0xff is a couple of bits too
big.

> +	ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);
> +
> +	return ag71xx_mdio_wait_busy(ag);
> +}

> +static void ag71xx_link_adjust(struct ag71xx *ag, bool update)
> +{
> +	struct net_device *ndev = ag->ndev;
> +	struct phy_device *phydev = ndev->phydev;
> +	u32 cfg2;
> +	u32 ifctl;
> +	u32 fifo5;
> +
> +	if (!phydev->link && update) {
> +		ag71xx_hw_stop(ag);
> +		netif_carrier_off(ag->ndev);

phylib will take care of the carrier for you.

       Andrew
Andrew Lunn May 20, 2019, 12:33 a.m. UTC | #2
> +config AG71XX
> +	tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
> +	depends on ATH79
> +	select PHYLIB
> +	select MDIO_BITBANG

I don't see any need for MDIO_BITBANG.

  Andrew
Oleksij Rempel May 20, 2019, 7:05 a.m. UTC | #3
On 20.05.19 02:33, Andrew Lunn wrote:
> Hi Oleksij
> 
>> +static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg)
>> +{
>> +	struct ag71xx *ag = bus->priv;
>> +	struct net_device *ndev = ag->ndev;
>> +	int err;
>> +	int ret;
>> +
>> +	err = ag71xx_mdio_wait_busy(ag);
>> +	if (err)
>> +		return err;
>> +
>> +	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
> 
> It looks like you have not removed this.

done.

> 
>> +	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
>> +			((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
>> +	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
>> +
>> +	err = ag71xx_mdio_wait_busy(ag);
>> +	if (err)
>> +		return err;
>> +
>> +	ret = ag71xx_rr(ag, AG71XX_REG_MII_STATUS);
>> +	/*
>> +	 * ar9331 doc: bits 31:16 are reserved and must be must be written
>> +	 * with zero.
>> +	 */
>> +	ret &= 0xffff;
>> +	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
> 
> Or this.

this one is needed. MII_CMD_WRITE is a wrong name, it is actually disabling MII_CMD_READ mode.

> 
>> +
>> +	netif_dbg(ag, link, ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n",
>> +		  addr, reg, ret);
>> +
>> +	return ret;
>> +}
>> +
>> +static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg,
>> +				 u16 val)
>> +{
>> +	struct ag71xx *ag = bus->priv;
>> +	struct net_device *ndev = ag->ndev;
>> +
>> +	netif_dbg(ag, link, ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n",
>> +		  addr, reg, val);
>> +
>> +	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
>> +			((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
> 
> addr have the vale 0-31. So a mask of 0xff is a couple of bits too
> big.

done

> 
>> +	ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);
>> +
>> +	return ag71xx_mdio_wait_busy(ag);
>> +}
> 
>> +static void ag71xx_link_adjust(struct ag71xx *ag, bool update)
>> +{
>> +	struct net_device *ndev = ag->ndev;
>> +	struct phy_device *phydev = ndev->phydev;
>> +	u32 cfg2;
>> +	u32 ifctl;
>> +	u32 fifo5;
>> +
>> +	if (!phydev->link && update) {
>> +		ag71xx_hw_stop(ag);
>> +		netif_carrier_off(ag->ndev);
> 
> phylib will take care of the carrier for you.

done

>         Andrew

thx!

Kind regards,
Oleksij Rempel