[v3,00/11] Add support for Orange Pi 3
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Message ID 20190411101951.30223-1-megous@megous.com
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  • Add support for Orange Pi 3
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Ondřej Jirman April 11, 2019, 10:19 a.m. UTC
From: Ondrej Jirman <megous@megous.com>

This series implements support for Xunlong Orange Pi 3 board.

Unfortunately, this board needs some small driver patches, so I have
split the boards DT patch into chunks that require patches for drivers
in various subsystems.

Suggested merging plan/dependencies:

- Pinctrl and stmmac patches are needed for ethernet support.
  (patches 1-5)
- HDMI support was changed, please review. (patches 6-8)
- brcmfmac patch 9, fixing firmware file selection, can be merged
  now, after review, as it doesn't depend on anything (please
  review :))
- mmc1 pinconf (patch 10) can probably be merged now, too (it will
  certainly be used soon by all the other WiFi featuring boards
  based on H6)
- WiFi dts patch will have to wait for H6 RTC patches, which in turn
  depend on ChenYu's RTC series, to be merged. That will take a
  while yet. I'm just keeping it in the series for completness.
  (patch 11)

This patch is also needed to not get segfault on boot (it was already
merged): 
  https://lkml.org/lkml/2019/4/5/856

Changes in v2:
- added dt-bindings documentation for the board's compatible string
  (suggested by Clement)
- addressed checkpatch warnings and code formatting issues (on Maxime's
  suggestions)
- stmmac: dropped useless parenthesis, reworded description of the patch
  (suggested by Sergei)
- drop useles dev_info() about the selected io bias voltage
- docummented io voltage bias selection variant macros
- wifi: marked WiFi DTS patch and realted mmc1_pins as "DO NOT MERGE",
  because wifi depends on H6 RTC support that's not merged yet (suggested
  by Clement)
- added missing signed-of-bys
- changed &usb2otg dr_mode to otg, and added a note about VBUS
- improved wording of HDMI driver's DDC power supply patch

Changes in v3:
- dropped already applied patches
- changed pinctrl I/O bias selection constants to enum and renamed
- added /omit-if-no-ref/ to mmc1_pins
- made mmc1_pins default pinconf for mmc1 in H6 dtsi
- move ddc-supply to HDMI connector node, updated patch descriptions,
  changed dt-bindings docs

Please take a look.

thank you and regards,
  Ondrej Jirman

Icenowy Zheng (2):
  net: stmmac: sun8i: add support for Allwinner H6 EMAC
  net: stmmac: sun8i: force select external PHY when no internal one

Ondrej Jirman (9):
  pinctrl: sunxi: Prepare for alternative bias voltage setting methods
  pinctrl: sunxi: Support I/O bias voltage setting on H6
  arm64: dts: allwinner: orange-pi-3: Enable ethernet
  dt-bindings: display: hdmi-connector: Add DDC power supply
  drm: sun4i: Add support for enabling DDC I2C bus power to dw_hdmi glue
  arm64: dts: allwinner: orange-pi-3: Enable HDMI output
  brcmfmac: Loading the correct firmware for brcm43456
  arm64: dts: allwinner: h6: Add MMC1 pins
  [DO NOT MERGE] arm64: dts: allwinner: orange-pi-3: Enable WiFi

 .../display/connector/hdmi-connector.txt      |   1 +
 .../dts/allwinner/sun50i-h6-orangepi-3.dts    | 127 ++++++++++++++++++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  11 ++
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c         |  60 ++++++++-
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h         |   2 +
 .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c |  21 +++
 .../broadcom/brcm80211/brcmfmac/sdio.c        |   4 +-
 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c     |   2 +-
 drivers/pinctrl/sunxi/pinctrl-sunxi.c         |  56 +++++---
 drivers/pinctrl/sunxi/pinctrl-sunxi.h         |  14 +-
 11 files changed, 275 insertions(+), 24 deletions(-)

Comments

Julian Calaby April 11, 2019, 10:34 a.m. UTC | #1
Hi Ondrej

On Thu, Apr 11, 2019 at 8:19 PM megous via linux-sunxi
<linux-sunxi@googlegroups.com> wrote:
>
> From: Ondrej Jirman <megous@megous.com>
>
> H6 has a different I/O voltage bias setting method than A80. Prepare
> existing code for using alternative bias voltage setting methods.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> index ee15ab067b5f..4bfc8a6d9dce 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> @@ -95,6 +95,13 @@
>  #define PINCTRL_SUN7I_A20      BIT(7)
>  #define PINCTRL_SUN8I_R40      BIT(8)
>
> +enum sunxi_desc_bias_voltage {
> +       BIAS_VOLTAGE_NONE,
> +       /* Bias voltage configuration is done through
> +        * Pn_GRP_CONFIG registers, as seen on A80 SoC. */
> +       BIAS_VOLTAGE_GRP_CONFIG,
> +};
> +
>  struct sunxi_desc_function {
>         unsigned long   variant;
>         const char      *name;
> @@ -117,7 +124,7 @@ struct sunxi_pinctrl_desc {
>         const unsigned int              *irq_bank_map;
>         bool                            irq_read_needs_mux;
>         bool                            disable_strict_mode;
> -       bool                            has_io_bias_cfg;
> +       int                             io_bias_cfg_variant;

Shouldn't we be defining this field using the enum rather than as an int?

Thanks,
Ondřej Jirman April 11, 2019, 10:44 a.m. UTC | #2
On Thu, Apr 11, 2019 at 08:34:33PM +1000, Julian Calaby wrote:
> Hi Ondrej
> 
> On Thu, Apr 11, 2019 at 8:19 PM megous via linux-sunxi
> <linux-sunxi@googlegroups.com> wrote:
> >
> > From: Ondrej Jirman <megous@megous.com>
> >
> > H6 has a different I/O voltage bias setting method than A80. Prepare
> > existing code for using alternative bias voltage setting methods.
> >
> > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> > index ee15ab067b5f..4bfc8a6d9dce 100644
> > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> > @@ -95,6 +95,13 @@
> >  #define PINCTRL_SUN7I_A20      BIT(7)
> >  #define PINCTRL_SUN8I_R40      BIT(8)
> >
> > +enum sunxi_desc_bias_voltage {
> > +       BIAS_VOLTAGE_NONE,
> > +       /* Bias voltage configuration is done through
> > +        * Pn_GRP_CONFIG registers, as seen on A80 SoC. */
> > +       BIAS_VOLTAGE_GRP_CONFIG,
> > +};
> > +
> >  struct sunxi_desc_function {
> >         unsigned long   variant;
> >         const char      *name;
> > @@ -117,7 +124,7 @@ struct sunxi_pinctrl_desc {
> >         const unsigned int              *irq_bank_map;
> >         bool                            irq_read_needs_mux;
> >         bool                            disable_strict_mode;
> > -       bool                            has_io_bias_cfg;
> > +       int                             io_bias_cfg_variant;
> 
> Shouldn't we be defining this field using the enum rather than as an int?

Yes, thank you, I fixed it for v4.

regards,
  	o.

> Thanks,
> 
> -- 
> Julian Calaby
> 
> Email: julian.calaby@gmail.com
> Profile: http://www.google.com/profiles/julian.calaby/
Maxime Ripard April 11, 2019, 12:22 p.m. UTC | #3
Hi,

On Thu, Apr 11, 2019 at 12:19:44PM +0200, megous@megous.com wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> H6 SoC has a "pio group withstand voltage mode" register (datasheet
> description), that needs to be used to select either 1.8V or 3.3V I/O mode,
> based on what voltage is powering the respective pin banks and is thus used
> for I/O signals.
>
> Add support for configuring this register according to the voltage of the
> pin bank regulator (if enabled).
>
> This is similar to the support for I/O bias voltage setting patch for A80
> and the same concerns apply. See:
>
>   commit 402bfb3c1352 ("Support I/O bias voltage setting on A80")
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> ---
>  drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c |  1 +
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c     | 11 +++++++++++
>  drivers/pinctrl/sunxi/pinctrl-sunxi.h     |  5 +++++
>  3 files changed, 17 insertions(+)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
> index ef4268cc6227..3cc1121589c9 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
> @@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
>  	.irq_banks = 4,
>  	.irq_bank_map = h6_irq_bank_map,
>  	.irq_read_needs_mux = true,
> +	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
>  };
>
>  static int h6_pinctrl_probe(struct platform_device *pdev)
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 98c4de5f4019..0cbca30b75dc 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -614,6 +614,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
>  					 unsigned pin,
>  					 struct regulator *supply)
>  {
> +	unsigned short bank = pin / PINS_PER_BANK;
> +	unsigned long flags;
>  	u32 val, reg;
>  	int uV;
>
> @@ -651,6 +653,15 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
>  		reg &= ~IO_BIAS_MASK;
>  		writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
>  		return 0;
> +	case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
> +		val = uV <= 1800000 ? 1 : 0;
> +
> +		raw_spin_lock_irqsave(&pctl->lock, flags);
> +		reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
> +		reg &= ~(1 << bank);
> +		writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
> +		raw_spin_unlock_irqrestore(&pctl->lock, flags);
> +		return 0;
>  	default:
>  		return -EINVAL;
>  	}
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> index 4bfc8a6d9dce..36186906f0a7 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
> @@ -95,11 +95,16 @@
>  #define PINCTRL_SUN7I_A20	BIT(7)
>  #define PINCTRL_SUN8I_R40	BIT(8)
>
> +#define PIO_POW_MOD_SEL_REG	0x340
> +
>  enum sunxi_desc_bias_voltage {
>  	BIAS_VOLTAGE_NONE,
>  	/* Bias voltage configuration is done through
>  	 * Pn_GRP_CONFIG registers, as seen on A80 SoC. */
>  	BIAS_VOLTAGE_GRP_CONFIG,
> +	/* Bias voltage is set through PIO_POW_MOD_SEL_REG
> +	 * register, as seen on H6 SoC, for example. */

That's not the proper comment style.

Once fixed, this patch and the previous is
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Maxime Ripard April 11, 2019, 12:25 p.m. UTC | #4
On Thu, Apr 11, 2019 at 12:19:47PM +0200, megous@megous.com wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> Orange Pi 3 board requires enabling DDC I2C bus via some GPIO connected
> transistors, before the bus can be used.
>
> Model this as a power supply for DDC bus on the HDMI connector connected
> to the output port (port 1) of the HDMI controller.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> ---
>  drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 60 ++++++++++++++++++++++++++-
>  drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h |  2 +
>  2 files changed, 60 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> index 39d8509d96a0..1b6ffba41177 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> @@ -98,6 +98,30 @@ static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm,
>  	return crtcs;
>  }
>
> +static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev,
> +					     struct platform_device **pdev_out)
> +{
> +	struct platform_device* pdev;

This doesn't respect the guidelines.

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
Chen-Yu Tsai April 12, 2019, 11:05 a.m. UTC | #5
On Thu, Apr 11, 2019 at 6:19 PM megous via linux-sunxi
<linux-sunxi@googlegroups.com> wrote:
>
> From: Ondrej Jirman <megous@megous.com>
>
> This series implements support for Xunlong Orange Pi 3 board.
>
> Unfortunately, this board needs some small driver patches, so I have
> split the boards DT patch into chunks that require patches for drivers
> in various subsystems.
>
> Suggested merging plan/dependencies:
>
> - Pinctrl and stmmac patches are needed for ethernet support.
>   (patches 1-5)
> - HDMI support was changed, please review. (patches 6-8)
> - brcmfmac patch 9, fixing firmware file selection, can be merged
>   now, after review, as it doesn't depend on anything (please
>   review :))
> - mmc1 pinconf (patch 10) can probably be merged now, too (it will
>   certainly be used soon by all the other WiFi featuring boards
>   based on H6)
> - WiFi dts patch will have to wait for H6 RTC patches, which in turn
>   depend on ChenYu's RTC series, to be merged. That will take a
>   while yet. I'm just keeping it in the series for completness.
>   (patch 11)

Unfortunately I will not have time to tackle this for the next release.
Furthermore, I'd like to do this after the new clk parenting stuff lands.
Otherwise it's going to be a mess, as the clock tree is a bit convoluted
compared to previous SoCs.

ChenYu
Ondřej Jirman April 12, 2019, 12:10 p.m. UTC | #6
Hello ChenYu,

On Fri, Apr 12, 2019 at 07:05:05PM +0800, Chen-Yu Tsai wrote:
> On Thu, Apr 11, 2019 at 6:19 PM megous via linux-sunxi
> <linux-sunxi@googlegroups.com> wrote:
> >
> > From: Ondrej Jirman <megous@megous.com>
> >
> > This series implements support for Xunlong Orange Pi 3 board.
> >
> > Unfortunately, this board needs some small driver patches, so I have
> > split the boards DT patch into chunks that require patches for drivers
> > in various subsystems.
> >
> > Suggested merging plan/dependencies:
> >
> > - Pinctrl and stmmac patches are needed for ethernet support.
> >   (patches 1-5)
> > - HDMI support was changed, please review. (patches 6-8)
> > - brcmfmac patch 9, fixing firmware file selection, can be merged
> >   now, after review, as it doesn't depend on anything (please
> >   review :))
> > - mmc1 pinconf (patch 10) can probably be merged now, too (it will
> >   certainly be used soon by all the other WiFi featuring boards
> >   based on H6)
> > - WiFi dts patch will have to wait for H6 RTC patches, which in turn
> >   depend on ChenYu's RTC series, to be merged. That will take a
> >   while yet. I'm just keeping it in the series for completness.
> >   (patch 11)
> 
> Unfortunately I will not have time to tackle this for the next release.
> Furthermore, I'd like to do this after the new clk parenting stuff lands.
> Otherwise it's going to be a mess, as the clock tree is a bit convoluted
> compared to previous SoCs.

I've sent out a patch series that addresses part of that for now.

So perhaps we can start with that and incrementally get to a full support,
of H6's complexities around clocks managed by RTC.

thanks,
	o.

> ChenYu
> 
> _______________________________________________
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