| Message ID | 1554969262-15028-1-git-send-email-cv-dong@jinso.co.jp |
|---|---|
| Headers | show |
| Series | Add more support to the RZ/G1C (r8a77470) SoC | expand |
Hello Cao, > From: devicetree-owner@vger.kernel.org <devicetree-owner@vger.kernel.org> > On Behalf Of Cao Van Dong > Sent: 11 April 2019 08:54 > > Dear everyone, > > This series adds HSCIF,MSIOF,PWM,CAN,VIN,Audio,Audio- > DMAC,Ether,VSP,FDP1,LVDS support > for the RZ/G1C (r8a77470) SoC. It is based on the renesas-drivers-2019-04-02- > v5.1-rc3 tag Thank you for your work to upstream more support for the RZ/G1C! > of renesas-drivers tree. Currently, I only add patches to the tree and compiled. > Unfortunately, RZ/G1C board is not available, so I have not tested these patches > on this board yet. > > cc Biju, > I know it is very difficult. however I still want to ask if you can help me test > them? The problem here is that Biju and the team only have iwg23s-sbc boards [1], which only expose these interfaces on external headers, in many cases without the require transceivers etc., meaning that testing is difficult. This is why we omitted them from the initial RZ/G1C upstreaming. Some interfaces are pretty low risk, so the maintainers may well accept some of your patches without testing I guess? [1] https://www.iwavesystems.com/product/single-board-computer/rzg1c/rz-g1c-single-board-computer.html > If possible, I will send the .dts file separately to you. I think you'd also need PFC changes. Kind regards, Chris > Because I am known you can be available this board. Thanks! > > Cao Van Dong (20): > ARM: dts: r8a77470: Add HSCIF support > ARM: dts: r8a77470: Add MSIOF support > ARM: dts: r8a77470: Add PWM support > ARM: dts: r8a77470: Add CAN support > ARM: dts: r8a77470: Add VIN support > ARM: dts: r8a77470: Add Audio support > ARM: dts: r8a77470: Add Audio-DMAC support > ARM: dts: r8a77470: Add Ether support > ARM: dts: r8a77470: Add VSP support > ARM: dts: r8a77470: Add FDP1 support > ARM: dts: r8a77470: Add LVDS support > ARM: dts: r8a77470: Add audio clocks > ARM: dts: r8a77470: Add can clocks > dt-bindings: display: renesas: lvds: Add r8a77470 support > media: dt-bindings: media: rcar_vin: Document r8a77470 bindings > ASoC: rsnd: Document r8a77470 bindings > dt-bindings: pwm: Document r8a77470 bindings > sh_eth: Document r8a77470 bindings > spi: sh-msiof: Document r8a77470 bindings > dt-bindings: can: rcar_can: Document r8a77470 bindings > > .../bindings/display/bridge/renesas,lvds.txt | 1 + > .../devicetree/bindings/media/rcar_vin.txt | 1 + > .../devicetree/bindings/net/can/rcar_can.txt | 1 + > Documentation/devicetree/bindings/net/sh_eth.txt | 1 + > .../devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 + > .../devicetree/bindings/sound/renesas,rsnd.txt | 1 + > Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 + > arch/arm/boot/dts/r8a77470.dtsi | 608 +++++++++++++++++++++ > drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 + > 9 files changed, 616 insertions(+) > > -- > 2.7.4
Hi Cao, On 2019-04-11 16:54:02 +0900, Cao Van Dong wrote: > Dear everyone, > > This series adds HSCIF,MSIOF,PWM,CAN,VIN,Audio,Audio-DMAC,Ether,VSP,FDP1,LVDS support > for the RZ/G1C (r8a77470) SoC. It is based on the renesas-drivers-2019-04-02-v5.1-rc3 tag > of renesas-drivers tree. Currently, I only add patches to the tree and compiled. > Unfortunately, RZ/G1C board is not available, so I have not tested these patches on this board yet. > > cc Biju, > I know it is very difficult. however I still want to ask if you can help me test them? > If possible, I will send the .dts file separately to you. > Because I am known you can be available this board. Thanks! > > Cao Van Dong (20): > ARM: dts: r8a77470: Add HSCIF support > ARM: dts: r8a77470: Add MSIOF support > ARM: dts: r8a77470: Add PWM support > ARM: dts: r8a77470: Add CAN support > ARM: dts: r8a77470: Add VIN support The changes for VIN looks OK but as Chris points out it would be nice if they could be tested. > ARM: dts: r8a77470: Add Audio support > ARM: dts: r8a77470: Add Audio-DMAC support > ARM: dts: r8a77470: Add Ether support > ARM: dts: r8a77470: Add VSP support > ARM: dts: r8a77470: Add FDP1 support > ARM: dts: r8a77470: Add LVDS support > ARM: dts: r8a77470: Add audio clocks > ARM: dts: r8a77470: Add can clocks > dt-bindings: display: renesas: lvds: Add r8a77470 support > media: dt-bindings: media: rcar_vin: Document r8a77470 bindings > ASoC: rsnd: Document r8a77470 bindings > dt-bindings: pwm: Document r8a77470 bindings > sh_eth: Document r8a77470 bindings > spi: sh-msiof: Document r8a77470 bindings > dt-bindings: can: rcar_can: Document r8a77470 bindings Nit-pick: I would first add the bindings to the documentation and then to the dts files. > > .../bindings/display/bridge/renesas,lvds.txt | 1 + > .../devicetree/bindings/media/rcar_vin.txt | 1 + > .../devicetree/bindings/net/can/rcar_can.txt | 1 + > Documentation/devicetree/bindings/net/sh_eth.txt | 1 + > .../devicetree/bindings/pwm/renesas,pwm-rcar.txt | 1 + > .../devicetree/bindings/sound/renesas,rsnd.txt | 1 + > Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 + > arch/arm/boot/dts/r8a77470.dtsi | 608 +++++++++++++++++++++ > drivers/gpu/drm/rcar-du/rcar_lvds.c | 1 + > 9 files changed, 616 insertions(+) > > -- > 2.7.4 >
On Thu, Apr 11, 2019 at 04:54:04PM +0900, Cao Van Dong wrote: > Add msiof{0|1|2} nodes to dtsi for MSIOF support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> > --- > arch/arm/boot/dts/r8a77470.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index 60bd79f..08a0b15 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -20,6 +20,9 @@ > i2c2 = &i2c2; > i2c3 = &i2c3; > i2c4 = &i2c4; > + spi1 = &msiof0; > + spi2 = &msiof1; > + spi3 = &msiof2; > }; Please do not add new aliases, we are moving away from this approach. Otherwise the patch looks good to me. > > cpus { > @@ -636,6 +639,54 @@ > status = "disabled"; > }; > > + msiof0: spi@e6e20000 { > + compatible = "renesas,msiof-r8a77470", > + "renesas,rcar-gen2-msiof"; > + reg = <0 0xe6e20000 0 0x0064>; > + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 000>; > + dmas = <&dmac0 0x51>, <&dmac0 0x52>, > + <&dmac1 0x51>, <&dmac1 0x52>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + #address-cells = <1>; > + #size-cells = <0>; > + resets = <&cpg 000>; > + status = "disabled"; > + }; > + > + msiof1: spi@e6e10000 { > + compatible = "renesas,msiof-r8a77470", > + "renesas,rcar-gen2-msiof"; > + reg = <0 0xe6e10000 0 0x0064>; > + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 208>; > + dmas = <&dmac0 0x55>, <&dmac0 0x56>, > + <&dmac1 0x55>, <&dmac1 0x56>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + #address-cells = <1>; > + #size-cells = <0>; > + resets = <&cpg 208>; > + status = "disabled"; > + }; > + > + msiof2: spi@e6e00000 { > + compatible = "renesas,msiof-r8a77470", > + "renesas,rcar-gen2-msiof"; > + reg = <0 0xe6e00000 0 0x0064>; > + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 205>; > + dmas = <&dmac0 0x41>, <&dmac0 0x42>, > + <&dmac1 0x41>, <&dmac1 0x42>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + #address-cells = <1>; > + #size-cells = <0>; > + resets = <&cpg 205>; > + status = "disabled"; > + }; > + > sdhi0: sd@ee100000 { > compatible = "renesas,sdhi-r8a77470", > "renesas,rcar-gen2-sdhi"; > -- > 2.7.4 >
Hi Dong-san, On Thu, Apr 11, 2019 at 04:54:06PM +0900, Cao Van Dong wrote: > Add can{0|1} nodes to dtsi for CAN support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> > --- > arch/arm/boot/dts/r8a77470.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index 7d1fe2f..97c51c5 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -757,6 +757,32 @@ > status = "disabled"; > }; > > + can0: can@e6e80000 { > + compatible = "renesas,can-r8a77470", > + "renesas,rcar-gen2-can"; > + reg = <0 0xe6e80000 0 0x1000>; > + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 916>, > + <&cpg CPG_CORE R8A77470_CLK_RCAN>, <&can_clk>; > + clock-names = "clkp1", "clkp2", "can_clk"; This patch makes use of can_clk which does not exist. I think a good solution to this problem would be to squash the following patch into this one: [PATCH v2 13/20] ARM: dts: r8a77470: Add can clocks > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + resets = <&cpg 916>; > + status = "disabled"; > + }; > + > + can1: can@e6e88000 { > + compatible = "renesas,can-r8a77470", > + "renesas,rcar-gen2-can"; > + reg = <0 0xe6e88000 0 0x1000>; > + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 915>, > + <&cpg CPG_CORE R8A77470_CLK_RCAN>, <&can_clk>; > + clock-names = "clkp1", "clkp2", "can_clk"; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + resets = <&cpg 915>; > + status = "disabled"; > + }; > + > sdhi0: sd@ee100000 { > compatible = "renesas,sdhi-r8a77470", > "renesas,rcar-gen2-sdhi"; > -- > 2.7.4 >
On Thu, Apr 11, 2019 at 04:54:07PM +0900, Cao Van Dong wrote: > Add vin{0|1} nodes to dtsi for VIN support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> > --- > arch/arm/boot/dts/r8a77470.dtsi | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index 97c51c5..7d47d04 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -23,6 +23,8 @@ > spi1 = &msiof0; > spi2 = &msiof1; > spi3 = &msiof2; > + vin0 = &vin0; > + vin1 = &vin1; > }; Please do not add aliases like this. I will go ahead and apply v1 of this patch which did not have the aliases. > > cpus { > @@ -783,6 +785,28 @@ > status = "disabled"; > }; > > + vin0: video@e6ef0000 { > + compatible = "renesas,vin-r8a77470", > + "renesas,rcar-gen2-vin"; > + reg = <0 0xe6ef0000 0 0x1000>; > + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 811>; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + resets = <&cpg 811>; > + status = "disabled"; > + }; > + > + vin1: video@e6ef1000 { > + compatible = "renesas,vin-r8a77470", > + "renesas,rcar-gen2-vin"; > + reg = <0 0xe6ef1000 0 0x1000>; > + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 810>; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + resets = <&cpg 810>; > + status = "disabled"; > + }; > + > sdhi0: sd@ee100000 { > compatible = "renesas,sdhi-r8a77470", > "renesas,rcar-gen2-sdhi"; > -- > 2.7.4 >
On Thu, Apr 11, 2019 at 04:54:08PM +0900, Cao Van Dong wrote: > Add rcar_sound node to dtsi for Audio support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> This patch makes use of nodes added by subsequent patches. Please make sure that all patches compile cleanly in the order they are supplied. In this case a good solution may be to to squash the following patches into this patch: [PATCH v2 07/20] ARM: dts: r8a77470: Add Audio-DMAC support [PATCH v2 12/20] ARM: dts: r8a77470: Add audio clocks > --- > arch/arm/boot/dts/r8a77470.dtsi | 261 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 261 insertions(+) > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index 7d47d04..a5a1918 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -807,6 +807,267 @@ > status = "disabled"; > }; > > + rcar_sound: sound@ec500000 { > + /* > + * #sound-dai-cells is required > + * > + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; > + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; > + */ > + compatible = "renesas,rcar_sound-r8a77470", > + "renesas,rcar_sound-gen2"; > + reg = <0 0xec500000 0 0x1000>, /* SCU */ > + <0 0xec5a0000 0 0x100>, /* ADG */ > + <0 0xec540000 0 0x1000>, /* SSIU */ > + <0 0xec541000 0 0x280>, /* SSI */ > + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ > + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; > + > + clocks = <&cpg CPG_MOD 1005>, > + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, > + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, > + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, > + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, > + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, > + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, > + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, > + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, > + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, > + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, > + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, > + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, > + <&cpg CPG_CORE R8A77470_CLK_M2>; > + clock-names = "ssi-all", > + "ssi.9", "ssi.8", "ssi.7", "ssi.6", > + "ssi.5", "ssi.4", "ssi.3", "ssi.2", > + "ssi.1", "ssi.0", > + "src.6", "src.5", "src.4", "src.3", > + "src.2", "src.1", > + "ctu.0", "ctu.1", > + "mix.0", "mix.1", > + "dvc.0", "dvc.1", > + "clk_a", "clk_b", "clk_c", "clk_i"; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + resets = <&cpg 1005>, > + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, > + <&cpg 1009>, <&cpg 1010>, <&cpg 1011>, > + <&cpg 1012>, <&cpg 1013>, <&cpg 1014>, > + <&cpg 1015>; > + reset-names = "ssi-all", > + "ssi.9", "ssi.8", "ssi.7", "ssi.6", > + "ssi.5", "ssi.4", "ssi.3", "ssi.2", > + "ssi.1", "ssi.0"; > + > + status = "disabled"; > + > + rcar_sound,dvc { > + dvc0: dvc-0 { > + dmas = <&audma0 0xbc>; > + dma-names = "tx"; > + }; > + dvc1: dvc-1 { > + dmas = <&audma0 0xbe>; > + dma-names = "tx"; > + }; > + }; > + > + rcar_sound,mix { > + mix0: mix-0 { }; > + mix1: mix-1 { }; > + }; > + > + rcar_sound,ctu { > + ctu00: ctu-0 { }; > + ctu01: ctu-1 { }; > + ctu02: ctu-2 { }; > + ctu03: ctu-3 { }; > + ctu10: ctu-4 { }; > + ctu11: ctu-5 { }; > + ctu12: ctu-6 { }; > + ctu13: ctu-7 { }; > + }; > + > + rcar_sound,src { > + src-0 { > + status = "disabled"; > + }; > + src1: src-1 { > + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x87>, <&audma0 0x9c>; > + dma-names = "rx", "tx"; > + }; > + src2: src-2 { > + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x89>, <&audma0 0x9e>; > + dma-names = "rx", "tx"; > + }; > + src3: src-3 { > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x8b>, <&audma0 0xa0>; > + dma-names = "rx", "tx"; > + }; > + src4: src-4 { > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x8d>, <&audma0 0xb0>; > + dma-names = "rx", "tx"; > + }; > + src5: src-5 { > + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x8f>, <&audma0 0xb2>; > + dma-names = "rx", "tx"; > + }; > + src6: src-6 { > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x91>, <&audma0 0xb4>; > + dma-names = "rx", "tx"; > + }; > + }; > + > + rcar_sound,ssiu { > + ssiu00: ssiu-0 { > + dmas = <&audma0 0x15>, <&audma0 0x16>; > + dma-names = "rx", "tx"; > + }; > + ssiu01: ssiu-1 { > + dmas = <&audma0 0x35>, <&audma0 0x36>; > + dma-names = "rx", "tx"; > + }; > + ssiu02: ssiu-2 { > + dmas = <&audma0 0x37>, <&audma0 0x38>; > + dma-names = "rx", "tx"; > + }; > + ssiu03: ssiu-3 { > + dmas = <&audma0 0x47>, <&audma0 0x48>; > + dma-names = "rx", "tx"; > + }; > + ssiu10: ssiu-4 { > + dmas = <&audma0 0x3F>, <&audma0 0x40>; > + dma-names = "rx", "tx"; > + }; > + ssiu11: ssiu-5 { > + dmas = <&audma0 0x43>, <&audma0 0x44>; > + dma-names = "rx", "tx"; > + }; > + ssiu12: ssiu-6 { > + dmas = <&audma0 0x4F>, <&audma0 0x50>; > + dma-names = "rx", "tx"; > + }; > + ssiu13: ssiu-7 { > + dmas = <&audma0 0x53>, <&audma0 0x54>; > + dma-names = "rx", "tx"; > + }; > + ssiu20: ssiu-8 { > + dmas = <&audma0 0x49>, <&audma0 0x4a>; > + dma-names = "rx", "tx"; > + }; > + ssiu21: ssiu-9 { > + dmas = <&audma0 0x4B>, <&audma0 0x4C>; > + dma-names = "rx", "tx"; > + }; > + ssiu22: ssiu-10 { > + dmas = <&audma0 0x57>, <&audma0 0x58>; > + dma-names = "rx", "tx"; > + }; > + ssiu23: ssiu-11 { > + dmas = <&audma0 0x59>, <&audma0 0x5A>; > + dma-names = "rx", "tx"; > + }; > + ssiu30: ssiu-12 { > + dmas = <&audma0 0x5F>, <&audma0 0x60>; > + dma-names = "rx", "tx"; > + }; > + ssiu40: ssiu-13 { > + dmas = <&audma0 0xC3>, <&audma0 0xC4>; > + dma-names = "rx", "tx"; > + }; > + ssiu50: ssiu-14 { > + dmas = <&audma0 0xC7>, <&audma0 0xC8>; > + dma-names = "rx", "tx"; > + }; > + ssiu60: ssiu-15 { > + dmas = <&audma0 0xCB>, <&audma0 0xCC>; > + dma-names = "rx", "tx"; > + }; > + ssiu70: ssiu-16 { > + dmas = <&audma0 0x63>, <&audma0 0x64>; > + dma-names = "rx", "tx"; > + }; > + ssiu80: ssiu-17 { > + dmas = <&audma0 0x67>, <&audma0 0x68>; > + dma-names = "rx", "tx"; > + }; > + ssiu90: ssiu-18 { > + dmas = <&audma0 0x6B>, <&audma0 0x6C>; > + dma-names = "rx", "tx"; > + }; > + ssiu91: ssiu-19 { > + dmas = <&audma0 0x6D>, <&audma0 0x6E>; > + dma-names = "rx", "tx"; > + }; > + ssiu92: ssiu-20 { > + dmas = <&audma0 0xCF>, <&audma0 0xCE>; > + dma-names = "rx", "tx"; > + }; > + ssiu93: ssiu-21 { > + dmas = <&audma0 0xEB>, <&audma0 0xEC>; > + dma-names = "rx", "tx"; > + }; > + }; > + > + rcar_sound,ssi { > + ssi0: ssi-0 { > + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x01>, <&audma0 0x02>; > + dma-names = "rx", "tx"; > + }; > + ssi1: ssi-1 { > + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x03>, <&audma0 0x04>; > + dma-names = "rx", "tx"; > + }; > + ssi2: ssi-2 { > + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x05>, <&audma0 0x06>; > + dma-names = "rx", "tx"; > + }; > + ssi3: ssi-3 { > + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x07>, <&audma0 0x08>; > + dma-names = "rx", "tx"; > + }; > + ssi4: ssi-4 { > + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x09>, <&audma0 0x0a>; > + dma-names = "rx", "tx"; > + }; > + ssi5: ssi-5 { > + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x0b>, <&audma0 0x0c>; > + dma-names = "rx", "tx"; > + }; > + ssi6: ssi-6 { > + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x0d>, <&audma0 0x0e>; > + dma-names = "rx", "tx"; > + }; > + ssi7: ssi-7 { > + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x0f>, <&audma0 0x10>; > + dma-names = "rx", "tx"; > + }; > + ssi8: ssi-8 { > + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x11>, <&audma0 0x12>; > + dma-names = "rx", "tx"; > + }; > + ssi9: ssi-9 { > + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&audma0 0x13>, <&audma0 0x14>; > + dma-names = "rx", "tx"; > + }; > + }; > + }; > + > sdhi0: sd@ee100000 { > compatible = "renesas,sdhi-r8a77470", > "renesas,rcar-gen2-sdhi"; > -- > 2.7.4 >
Hi Dong-san, On Thu, Apr 11, 2019 at 04:54:10PM +0900, Cao Van Dong wrote: > Add ether node to dtsi for Ether support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> > --- > arch/arm/boot/dts/r8a77470.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index 9fc9f6a..ae1dba0 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -1099,6 +1099,20 @@ > dma-channels = <13>; > }; > > + ether: ethernet@ee700000 { Nodes should be sorted by 1. Bus address 2. IP block type So ethernet@ee700000 should go after sd@ee100000. Otherwise this patch looks good to me. > + compatible = "renesas,ether-r8a77470", > + "renesas,rcar-gen2-ether"; > + reg = <0 0xee700000 0 0x400>; > + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 813>; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + resets = <&cpg 813>; > + phy-mode = "rmii"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > sdhi0: sd@ee100000 { > compatible = "renesas,sdhi-r8a77470", > "renesas,rcar-gen2-sdhi"; > -- > 2.7.4 >
On Thu, Apr 11, 2019 at 04:54:11PM +0900, Cao Van Dong wrote: > Add vsp nodes to dtsi for VSP support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> > --- > arch/arm/boot/dts/r8a77470.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index ae1dba0..2540bca 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -1113,6 +1113,24 @@ > status = "disabled"; > }; > > + vsp@fe928000 { > + compatible = "renesas,vsp1"; > + reg = <0 0xfe928000 0 0x8000>; > + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 131>; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + resets = <&cpg 131>; > + }; > + > + vsp@fe930000 { > + compatible = "renesas,vsp1"; > + reg = <0 0xfe930000 0 0x8000>; > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 128>; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + resets = <&cpg 128>; > + }; > + Nodes should be sorted by 1. Bus address 2. IP block tupe So the above vsp nodes should go after sd@ee100000. Otherwise this patch looks good to me. > sdhi0: sd@ee100000 { > compatible = "renesas,sdhi-r8a77470", > "renesas,rcar-gen2-sdhi"; > -- > 2.7.4 >
Hi Dong-san, On Thu, Apr 11, 2019 at 04:54:12PM +0900, Cao Van Dong wrote: > Add fdp1 node to dtsi for FDP1 support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> > --- > arch/arm/boot/dts/r8a77470.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi > index 2540bca..7881516 100644 > --- a/arch/arm/boot/dts/r8a77470.dtsi > +++ b/arch/arm/boot/dts/r8a77470.dtsi > @@ -1131,6 +1131,15 @@ > resets = <&cpg 128>; > }; > > + fdp1@fe940000 { > + compatible = "renesas,fdp1"; > + reg = <0 0xfe940000 0 0x2400>; > + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 119>; > + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; > + resets = <&cpg 119>; > + }; > + Nodes should be sorted by 1. Bus address 2. IP block tupe So the above vsp nodes should not go before sd@ee100000. Otherwise this patch looks good to me. > sdhi0: sd@ee100000 { > compatible = "renesas,sdhi-r8a77470", > "renesas,rcar-gen2-sdhi"; > -- > 2.7.4 >
On Thu, Apr 11, 2019 at 04:54:03PM +0900, Cao Van Dong wrote: > Add hscif{0|1|2} nodes to dtsi for HSCIF support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Thanks Dong-san, applied for inclusion in v5.2 with the changelog wrapped to 75 columns wide.
On Thu, Apr 11, 2019 at 04:54:05PM +0900, Cao Van Dong wrote: > Add pwm{0|1|2|3|4|5|6} nodes to dtsi for PWM support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Thanks Dong-san, applied for inclusion in v5.2 with the changelog wrapped to 75 columns wide.
On Thu, Apr 11, 2019 at 9:54 AM Cao Van Dong <cv-dong@jinso.co.jp> wrote: > Add hscif{0|1|2} nodes to dtsi for HSCIF support on the RZ/G1C (r8a77470) SoC. > > Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert