From patchwork Mon Apr 8 12:12:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kavyasree Kotagiri X-Patchwork-Id: 1080938 Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="3WKO6ydU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44d8SD05TNz9sQp for ; Mon, 8 Apr 2019 22:12:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726654AbfDHMM0 (ORCPT ); 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Mon, 8 Apr 2019 12:12:23 +0000 Received: from BY5PR11MB4119.namprd11.prod.outlook.com ([fe80::4454:7962:5f5a:72e9]) by BY5PR11MB4119.namprd11.prod.outlook.com ([fe80::4454:7962:5f5a:72e9%2]) with mapi id 15.20.1771.021; Mon, 8 Apr 2019 12:12:23 +0000 From: To: , , CC: , Subject: [PATCH v3 0/2] net: phy: mscc: Improvements to VSC8514 PHY driver Thread-Topic: [PATCH v3 0/2] net: phy: mscc: Improvements to VSC8514 PHY driver Thread-Index: AQHU7gRS9+D6myxtWEqJXTXi2XoV9g== Date: Mon, 8 Apr 2019 12:12:22 +0000 Message-ID: <20190408121158.14269-1-kavyasree.kotagiri@microchip.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: CO1PR15CA0092.namprd15.prod.outlook.com (2603:10b6:101:21::12) To BY5PR11MB4119.namprd11.prod.outlook.com (2603:10b6:a03:18f::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Kavyasree.Kotagiri@microchip.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [182.72.246.220] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cc721c38-3fcb-4e7e-50db-08d6bc1b748e x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: GBBS5PH6B11zWKDw4hDw4SwJnupjOmnrCcOhh/THyzmaERml5iKOMozQIcociV3vdidtadtO4OrokJOpoVdv0hDtpm99vOzDzpMl1vgOUg/NpDTETr1RtfDYpVUQfOoKqfefcNMDaTU6I3MI4hwT3p7V/dj1JnuDlKmeD1S+oI+qNdAu1spwup70K8wo+JkDSx13psR+0Dkfs0FIP3NMG39i6vZpr3Vm85e0Zhl4qq2MgZp2J79pn+Zz1fSDx+PfhSiQwbIn3BU3J0bnqX8UDpdRBRjCUcrmrpKShyxKNiTsKGrr2Q3wyoazlmJ726Dtay9S+Hbqe9eyevaS9Oj/mAv0n8XJrjZZ6lFY+3zfISrrYEKZC1WcPcHbbL7P5PQAKSED/ZfDyNxm6fL8QhO2cttHK5AKn6DiSYxQ2Bn+Xyg= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: cc721c38-3fcb-4e7e-50db-08d6bc1b748e X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Apr 2019 12:12:23.0500 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB3975 X-OriginatorOrg: microchip.com Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Kavya Sree Kotagiri The VSC8514 PHY is a 4-ports PHY that is 10/100/1000BASE-T, 100BASE-FX, 1000BASE-X, can communicate with the MAC via QSGMII. The MAC interface protocol for each port within QSGMII can be either 1000BASE-X or SGMII, if the QSGMII MAC that the VSC8514 is connecting to supports this functionality. VSC8514 also supports SGMII MAC-side autonegotiation on each individual port, downshifting, can set the blinking pattern of each of its 4 LEDs, SyncE, 1000BASE-T Ring Resiliency as well as HP Auto-MDIX detection. This patch series adds support for 10BASE-T, 100BASE-TX, and 1000BASE-T, QSGMII link with the MAC, downshifting, HP Auto-MDIX detection and blinking pattern for its 4 LEDs. The GPIO register bank is a set of registers that are common to all PHYs in the package. So any modification in any register of this bank affects all PHYs of the package. If the PHYs haven't been reset before booting the Linux kernel and were configured to use interrupts for e.g. link status updates, it is required to clear the interrupts mask register of all PHYs before being able to use interrupts with any PHY. The first PHY of the package that will be init will take care of clearing all PHYs interrupts mask registers. Thus, we need to keep track of the init sequence in the package, if it's already been done or if it's to be done. Most of the init sequence of a PHY of the package is common to all PHYs in the package, thus we use the SMI broadcast feature which enables us to propagate a write in one register of one PHY to all PHYs in the same package. This patch series adds support for VSC8514 in Microsemi driver(mscc.c) and removes support from Vitesse driver(vitesse.c). v3 - mscc: Used BIT(x) for PHY_MCB_S6G_WRITE and PHY_MCB_S6G_READ instead of hex. - mscc: Replaced magic numbers with proper constants. - mscc: Handled delays and timeouts at appropriate points. - mscc: Added comments/explanation where requested. v2 - mscc: Sorted varible declarations in reverse christmas tree order. v1 - Added 0/2 file. Kavya Sree (2): net: phy: mscc: add support for VSC8514 PHY net: phy: vitesse: Remove support for VSC8514 drivers/net/phy/Kconfig | 2 +- drivers/net/phy/mscc.c | 428 ++++++++++++++++++++++++++++++++++++++++ drivers/net/phy/vitesse.c | 12 ------------ 3 files changed, 429 insertions(+), 13 deletions(-)