From patchwork Wed Feb 6 03:32:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 1037321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=csie.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43vRqv0B1sz9sN9 for ; Wed, 6 Feb 2019 14:33:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727460AbfBFDdg (ORCPT ); Tue, 5 Feb 2019 22:33:36 -0500 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:33756 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726456AbfBFDcs (ORCPT ); Tue, 5 Feb 2019 22:32:48 -0500 Received: by wens.csie.org (Postfix, from userid 1000) id 8FC765FCDF; Wed, 6 Feb 2019 11:32:43 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Linus Walleij Cc: Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 0/9] ARM: sun9i: a80: Enable GMAC Date: Wed, 6 Feb 2019 11:32:30 +0800 Message-Id: <20190206033239.3619-1-wens@csie.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi everyone, On the Allwinner A80, the PIO pin controller includes configuration registers to set the I/O voltage. These must match the actual voltage provided externally. A mismatch results in signals not being passed through. With the new PIO pin-bank regulator supply support in place, we can tack on support for setting up these registers. This in turn allows us to enable the GMAC, which runs at a reduced 2.5V for RGMII, instead of the standard 3.0V or 3.3V. Please have a look. Regards ChenYu Chen-Yu Tsai (9): pinctrl: sunxi: Support I/O bias voltage setting on A80 ARM: dts: sun9i: a80-optimus: Add node for AXP809's unused dc1sw regulator ARM: dts: sun9i: a80-optimus: Add GPIO pin-bank regulator supplies ARM: dts: sun9i: cubieboard4: Add GPIO pin-bank regulator supplies ARM: dts: sun9i: Add GMAC clock node ARM: dts: sun9i: Add A80 GMAC gigabit ethernet controller node ARM: dts: sun9i: Add A80 GMAC RGMII pinmux setting ARM: dts: sun9i: a80-optimus: Enable GMAC ARM: dts: sun9i: cubieboard4: Enable GMAC arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 44 +++++++++++++- arch/arm/boot/dts/sun9i-a80-optimus.dts | 44 +++++++++++++- arch/arm/boot/dts/sun9i-a80.dtsi | 65 +++++++++++++++++++++ drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 1 + drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 1 + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 41 +++++++++++++ drivers/pinctrl/sunxi/pinctrl-sunxi.h | 12 ++++ 7 files changed, 202 insertions(+), 6 deletions(-)